<AVRPART><MODULE_LIST>[ADMIN:CORE:MEMORY:PACKAGE:INTERRUPT_VECTOR:FUSE:PROGRAMMING:LOCKBIT:IO_MODULE:ICE_SETTINGS]</MODULE_LIST><ADMIN>
<PART_NAME>ATtiny45</PART_NAME>
<SPEED>20MHZ</SPEED>
<BUILD>158</BUILD>
<RELEASE_STATUS>RELEASED</RELEASE_STATUS>
<SIGNATURE>
<ADDR000>$1E</ADDR000>
<ADDR001>$92</ADDR001>
<ADDR002>$06</ADDR002>
</SIGNATURE>
</ADMIN>
<CORE>
<CORE_VERSION>V2</CORE_VERSION>
<ID>AVRSimCoreV2.SimCoreV2</ID>
<NEW_INSTRUCTIONS>[lpm rd,z+]</NEW_INSTRUCTIONS>
<INSTRUCTIONS_NOT_SUPPORTED>[]</INSTRUCTIONS_NOT_SUPPORTED>
<RAMP_REGISTERS>[]</RAMP_REGISTERS>
<GP_REG_FILE>
<NMB_REG>32</NMB_REG>
<START_ADDR>$00</START_ADDR>
<X_REG_HIGH>$1B</X_REG_HIGH>
<X_REG_LOW>$1A</X_REG_LOW>
<Y_REG_HIGH>$1D</Y_REG_HIGH>
<Y_REG_LOW>$1C</Y_REG_LOW>
<Z_REG_HIGH>$1F</Z_REG_HIGH>
<Z_REG_LOW>$1E</Z_REG_LOW>
</GP_REG_FILE>
</CORE>
<MEMORY>
<ID>AVRSimMemory8bit.SimMemory8bit</ID>
<PROG_FLASH>4096</PROG_FLASH>
<EEPROM>256</EEPROM>
<INT_SRAM>
<SIZE>256</SIZE>
<START_ADDR>$60</START_ADDR>
</INT_SRAM>
<EXT_SRAM>
<SIZE>0</SIZE>
<START_ADDR>NA</START_ADDR>
</EXT_SRAM>
<IO_MEMORY>
<IO_START_ADDR>$00</IO_START_ADDR>
<IO_STOP_ADDR>$3F</IO_STOP_ADDR>
<EXT_IO_START_ADDR>NA</EXT_IO_START_ADDR>
<EXT_IO_STOP_ADDR>NA</EXT_IO_STOP_ADDR>
<MEM_START_ADDR>$20</MEM_START_ADDR>
<MEM_STOP_ADDR>$5F</MEM_STOP_ADDR>
<SREG>
<IO_ADDR>$3F</IO_ADDR>
<MEM_ADDR>$5F</MEM_ADDR>
<C_MASK>0x01</C_MASK><Z_MASK>0x02</Z_MASK><N_MASK>0x04</N_MASK><V_MASK>0x08</V_MASK><S_MASK>0x10</S_MASK><H_MASK>0x20</H_MASK><T_MASK>0x40</T_MASK><I_MASK>0x80</I_MASK></SREG>
<SPH>
<IO_ADDR>$3E</IO_ADDR>
<MEM_ADDR>$5E</MEM_ADDR>
<INIT>0x01</INIT>
<SP8_MASK>0x01</SP8_MASK></SPH>
<SPL>
<IO_ADDR>$3D</IO_ADDR>
<MEM_ADDR>$5D</MEM_ADDR>
<INIT>0x5F</INIT>
<SP0_MASK>0x01</SP0_MASK><SP1_MASK>0x02</SP1_MASK><SP2_MASK>0x04</SP2_MASK><SP3_MASK>0x08</SP3_MASK><SP4_MASK>0x10</SP4_MASK><SP5_MASK>0x20</SP5_MASK><SP6_MASK>0x40</SP6_MASK><SP7_MASK>0x80</SP7_MASK></SPL>
<GIMSK>
<IO_ADDR>$3B</IO_ADDR>
<MEM_ADDR>$5B</MEM_ADDR>
<PCIE_MASK>0x20</PCIE_MASK><INT0_MASK>0x40</INT0_MASK></GIMSK>
<GIFR>
<IO_ADDR>$3A</IO_ADDR>
<MEM_ADDR>$5A</MEM_ADDR>
<PCIF_MASK>0x20</PCIF_MASK><INTF0_MASK>0x40</INTF0_MASK></GIFR>
<TIMSK>
<IO_ADDR>$39</IO_ADDR>
<MEM_ADDR>$59</MEM_ADDR>
<TOIE0_MASK>0x02</TOIE0_MASK><OCIE0B_MASK>0x08</OCIE0B_MASK><OCIE0A_MASK>0x10</OCIE0A_MASK><TOIE1_MASK>0x04</TOIE1_MASK><OCIE1B_MASK>0x20</OCIE1B_MASK><OCIE1A_MASK>0x40</OCIE1A_MASK></TIMSK>
<TIFR>
<IO_ADDR>$38</IO_ADDR>
<MEM_ADDR>$58</MEM_ADDR>
<TOV0_MASK>0x02</TOV0_MASK><OCF0B_MASK>0x08</OCF0B_MASK><OCF0A_MASK>0x10</OCF0A_MASK><TOV1_MASK>0x04</TOV1_MASK><OCF1B_MASK>0x20</OCF1B_MASK><OCF1A_MASK>0x40</OCF1A_MASK></TIFR>
<SPMCSR>
<IO_ADDR>$37</IO_ADDR>
<MEM_ADDR>$57</MEM_ADDR>
<SPMEN_MASK>0x01</SPMEN_MASK><PGERS_MASK>0x02</PGERS_MASK><PGWRT_MASK>0x04</PGWRT_MASK><RFLB_MASK>0x08</RFLB_MASK><CTPB_MASK>0x10</CTPB_MASK></SPMCSR>
<MCUCR>
<IO_ADDR>$35</IO_ADDR>
<MEM_ADDR>$55</MEM_ADDR>
<ISC00_MASK>0x01</ISC00_MASK><ISC01_MASK>0x02</ISC01_MASK><SM0_MASK>0x08</SM0_MASK><SM1_MASK>0x10</SM1_MASK><SE_MASK>0x20</SE_MASK><PUD_MASK>0x40</PUD_MASK></MCUCR>
<MCUSR>
<IO_ADDR>$34</IO_ADDR>
<MEM_ADDR>$54</MEM_ADDR>
<PORF_MASK>0x01</PORF_MASK><EXTRF_MASK>0x02</EXTRF_MASK><BORF_MASK>0x04</BORF_MASK><WDRF_MASK>0x08</WDRF_MASK></MCUSR>
<TCCR0B>
<IO_ADDR>$33</IO_ADDR>
<MEM_ADDR>$53</MEM_ADDR>
<CS00_MASK>0x01</CS00_MASK><CS01_MASK>0x02</CS01_MASK><CS02_MASK>0x04</CS02_MASK><WGM02_MASK>0x08</WGM02_MASK><FOC0B_MASK>0x40</FOC0B_MASK><FOC0A_MASK>0x80</FOC0A_MASK></TCCR0B>
<TCNT0>
<IO_ADDR>$32</IO_ADDR>
<MEM_ADDR>$52</MEM_ADDR>
<TCNT0_0_MASK>0x01</TCNT0_0_MASK><TCNT0_1_MASK>0x02</TCNT0_1_MASK><TCNT0_2_MASK>0x04</TCNT0_2_MASK><TCNT0_3_MASK>0x08</TCNT0_3_MASK><TCNT0_4_MASK>0x10</TCNT0_4_MASK><TCNT0_5_MASK>0x20</TCNT0_5_MASK><TCNT0_6_MASK>0x40</TCNT0_6_MASK><TCNT0_7_MASK>0x80</TCNT0_7_MASK></TCNT0>
<OSCCAL>
<IO_ADDR>$31</IO_ADDR>
<MEM_ADDR>$51</MEM_ADDR>
<CAL0_MASK>0x01</CAL0_MASK><CAL1_MASK>0x02</CAL1_MASK><CAL2_MASK>0x04</CAL2_MASK><CAL3_MASK>0x08</CAL3_MASK><CAL4_MASK>0x10</CAL4_MASK><CAL5_MASK>0x20</CAL5_MASK><CAL6_MASK>0x40</CAL6_MASK><CAL7_MASK>0x80</CAL7_MASK></OSCCAL>
<TCCR1>
<IO_ADDR>$30</IO_ADDR>
<MEM_ADDR>$50</MEM_ADDR>
<CS10_MASK>0x01</CS10_MASK><CS11_MASK>0x02</CS11_MASK><CS12_MASK>0x04</CS12_MASK><CS13_MASK>0x08</CS13_MASK><COM1A0_MASK>0x10</COM1A0_MASK><COM1A1_MASK>0x20</COM1A1_MASK><PWM1A_MASK>0x40</PWM1A_MASK><CTC1_MASK>0x80</CTC1_MASK></TCCR1>
<TCNT1>
<IO_ADDR>$2F</IO_ADDR>
<MEM_ADDR>$4F</MEM_ADDR>
<TCNT1_0_MASK>0x01</TCNT1_0_MASK><TCNT1_1_MASK>0x02</TCNT1_1_MASK><TCNT1_2_MASK>0x04</TCNT1_2_MASK><TCNT1_3_MASK>0x08</TCNT1_3_MASK><TCNT1_4_MASK>0x10</TCNT1_4_MASK><TCNT1_5_MASK>0x20</TCNT1_5_MASK><TCNT1_6_MASK>0x40</TCNT1_6_MASK><TCNT1_7_MASK>0x80</TCNT1_7_MASK></TCNT1>
<OCR1A>
<IO_ADDR>$2E</IO_ADDR>
<MEM_ADDR>$4E</MEM_ADDR>
<OCR1A0_MASK>0x01</OCR1A0_MASK><OCR1A1_MASK>0x02</OCR1A1_MASK><OCR1A2_MASK>0x04</OCR1A2_MASK><OCR1A3_MASK>0x08</OCR1A3_MASK><OCR1A4_MASK>0x10</OCR1A4_MASK><OCR1A5_MASK>0x20</OCR1A5_MASK><OCR1A6_MASK>0x40</OCR1A6_MASK><OCR1A7_MASK>0x80</OCR1A7_MASK></OCR1A>
<OCR1C>
<IO_ADDR>$2D</IO_ADDR>
<MEM_ADDR>$4D</MEM_ADDR>
<OCR1C0_MASK>0x01</OCR1C0_MASK><OCR1C1_MASK>0x02</OCR1C1_MASK><OCR1C2_MASK>0x04</OCR1C2_MASK><OCR1C3_MASK>0x08</OCR1C3_MASK><OCR1C4_MASK>0x10</OCR1C4_MASK><OCR1C5_MASK>0x20</OCR1C5_MASK><OCR1C6_MASK>0x40</OCR1C6_MASK><OCR1C7_MASK>0x80</OCR1C7_MASK></OCR1C>
<GTCCR>
<IO_ADDR>$2C</IO_ADDR>
<MEM_ADDR>$4C</MEM_ADDR>
<PSR0_MASK>0x01</PSR0_MASK><TSM_MASK>0x80</TSM_MASK><PSR1_MASK>0x02</PSR1_MASK><FOC1A_MASK>0x04</FOC1A_MASK><FOC1B_MASK>0x08</FOC1B_MASK><COM1B0_MASK>0x10</COM1B0_MASK><COM1B1_MASK>0x20</COM1B1_MASK><PWM1B_MASK>0x40</PWM1B_MASK></GTCCR>
<OCR1B>
<IO_ADDR>$2B</IO_ADDR>
<MEM_ADDR>$4B</MEM_ADDR>
<OCR1B0_MASK>0x01</OCR1B0_MASK><OCR1B1_MASK>0x02</OCR1B1_MASK><OCR1B2_MASK>0x04</OCR1B2_MASK><OCR1B3_MASK>0x08</OCR1B3_MASK><OCR1B4_MASK>0x10</OCR1B4_MASK><OCR1B5_MASK>0x20</OCR1B5_MASK><OCR1B6_MASK>0x40</OCR1B6_MASK><OCR1B7_MASK>0x80</OCR1B7_MASK></OCR1B>
<TCCR0A>
<IO_ADDR>$2A</IO_ADDR>
<MEM_ADDR>$4A</MEM_ADDR>
<WGM00_MASK>0x01</WGM00_MASK><WGM01_MASK>0x02</WGM01_MASK><COM0B0_MASK>0x10</COM0B0_MASK><COM0B1_MASK>0x20</COM0B1_MASK><COM0A0_MASK>0x40</COM0A0_MASK><COM0A1_MASK>0x80</COM0A1_MASK></TCCR0A>
<OCR0A>
<IO_ADDR>$29</IO_ADDR>
<MEM_ADDR>$49</MEM_ADDR>
<OCR0_0_MASK>0x01</OCR0_0_MASK><OCR0_1_MASK>0x02</OCR0_1_MASK><OCR0_2_MASK>0x04</OCR0_2_MASK><OCR0_3_MASK>0x08</OCR0_3_MASK><OCR0_4_MASK>0x10</OCR0_4_MASK><OCR0_5_MASK>0x20</OCR0_5_MASK><OCR0_6_MASK>0x40</OCR0_6_MASK><OCR0_7_MASK>0x80</OCR0_7_MASK></OCR0A>
<OCR0B>
<IO_ADDR>$28</IO_ADDR>
<MEM_ADDR>$48</MEM_ADDR>
<OCR0_0_MASK>0x01</OCR0_0_MASK><OCR0_1_MASK>0x02</OCR0_1_MASK><OCR0_2_MASK>0x04</OCR0_2_MASK><OCR0_3_MASK>0x08</OCR0_3_MASK><OCR0_4_MASK>0x10</OCR0_4_MASK><OCR0_5_MASK>0x20</OCR0_5_MASK><OCR0_6_MASK>0x40</OCR0_6_MASK><OCR0_7_MASK>0x80</OCR0_7_MASK></OCR0B>
<PLLCSR>
<IO_ADDR>$27</IO_ADDR>
<MEM_ADDR>$47</MEM_ADDR>
<PLOCK_MASK>0x01</PLOCK_MASK><PLLE_MASK>0x02</PLLE_MASK><PCKE_MASK>0x04</PCKE_MASK><LSM_MASK>0x80</LSM_MASK></PLLCSR>
<CLKPR>
<IO_ADDR>$26</IO_ADDR>
<MEM_ADDR>$46</MEM_ADDR>
<CLKPS0_MASK>0x01</CLKPS0_MASK><CLKPS1_MASK>0x02</CLKPS1_MASK><CLKPS2_MASK>0x04</CLKPS2_MASK><CLKPS3_MASK>0x08</CLKPS3_MASK><CLKPCE_MASK>0x80</CLKPCE_MASK></CLKPR>
<DTVALA>
<IO_ADDR>$25</IO_ADDR>
<MEM_ADDR>$45</MEM_ADDR>
<DTVL0_MASK>0x01</DTVL0_MASK><DTVL1_MASK>0x02</DTVL1_MASK><DTVL2_MASK>0x04</DTVL2_MASK><DTVL3_MASK>0x08</DTVL3_MASK><DTVH0_MASK>0x10</DTVH0_MASK><DTVH1_MASK>0x20</DTVH1_MASK><DTVH2_MASK>0x40</DTVH2_MASK><DTVH3_MASK>0x80</DTVH3_MASK></DTVALA>
<DTVALB>
<IO_ADDR>$24</IO_ADDR>
<MEM_ADDR>$44</MEM_ADDR>
<DTVL0_MASK>0x01</DTVL0_MASK><DTVL1_MASK>0x02</DTVL1_MASK><DTVL2_MASK>0x04</DTVL2_MASK><DTVL3_MASK>0x08</DTVL3_MASK><DTVH0_MASK>0x10</DTVH0_MASK><DTVH1_MASK>0x20</DTVH1_MASK><DTVH2_MASK>0x40</DTVH2_MASK><DTVH3_MASK>0x80</DTVH3_MASK></DTVALB>
<DTPS>
<IO_ADDR>$23</IO_ADDR>
<MEM_ADDR>$43</MEM_ADDR>
<DTPS0_MASK>0x01</DTPS0_MASK><DTPS1_MASK>0x02</DTPS1_MASK></DTPS>
<DWDR>
<IO_ADDR>$22</IO_ADDR>
<MEM_ADDR>$42</MEM_ADDR>
<DWDR0_MASK>0x01</DWDR0_MASK><DWDR1_MASK>0x02</DWDR1_MASK><DWDR2_MASK>0x04</DWDR2_MASK><DWDR3_MASK>0x08</DWDR3_MASK><DWDR4_MASK>0x10</DWDR4_MASK><DWDR5_MASK>0x20</DWDR5_MASK><DWDR6_MASK>0x40</DWDR6_MASK><DWDR7_MASK>0x80</DWDR7_MASK></DWDR>
<WDTCR>
<IO_ADDR>$21</IO_ADDR>
<MEM_ADDR>$41</MEM_ADDR>
<WDP0_MASK>0x01</WDP0_MASK><WDP1_MASK>0x02</WDP1_MASK><WDP2_MASK>0x04</WDP2_MASK><WDE_MASK>0x08</WDE_MASK><WDCE_MASK>0x10</WDCE_MASK><WDP3_MASK>0x20</WDP3_MASK><WDIE_MASK>0x40</WDIE_MASK><WDIF_MASK>0x80</WDIF_MASK></WDTCR>
<PRR>
<IO_ADDR>$20</IO_ADDR>
<MEM_ADDR>$40</MEM_ADDR>
<PRADC_MASK>0x01</PRADC_MASK><PRUSI_MASK>0x02</PRUSI_MASK><PRTIM0_MASK>0x04</PRTIM0_MASK><PRTIM1_MASK>0x08</PRTIM1_MASK></PRR>
<EEARH>
<IO_ADDR>$1F</IO_ADDR>
<MEM_ADDR>$3F</MEM_ADDR>
<EEAR8_MASK>0x01</EEAR8_MASK></EEARH>
<EEARL>
<IO_ADDR>$1E</IO_ADDR>
<MEM_ADDR>$3E</MEM_ADDR>
<EEAR0_MASK>0x01</EEAR0_MASK><EEAR1_MASK>0x02</EEAR1_MASK><EEAR2_MASK>0x04</EEAR2_MASK><EEAR3_MASK>0x08</EEAR3_MASK><EEAR4_MASK>0x10</EEAR4_MASK><EEAR5_MASK>0x20</EEAR5_MASK><EEAR6_MASK>0x40</EEAR6_MASK><EEAR7_MASK>0x80</EEAR7_MASK></EEARL>
<EEDR>
<IO_ADDR>$1D</IO_ADDR>
<MEM_ADDR>$3D</MEM_ADDR>
<EEDR0_MASK>0x01</EEDR0_MASK><EEDR1_MASK>0x02</EEDR1_MASK><EEDR2_MASK>0x04</EEDR2_MASK><EEDR3_MASK>0x08</EEDR3_MASK><EEDR4_MASK>0x10</EEDR4_MASK><EEDR5_MASK>0x20</EEDR5_MASK><EEDR6_MASK>0x40</EEDR6_MASK><EEDR7_MASK>0x80</EEDR7_MASK></EEDR>
<EECR>
<IO_ADDR>$1C</IO_ADDR>
<MEM_ADDR>$3C</MEM_ADDR>
<EERE_MASK>0x01</EERE_MASK><EEPE_MASK>0x02</EEPE_MASK><EEMPE_MASK>0x04</EEMPE_MASK><EERIE_MASK>0x08</EERIE_MASK><EEPM0_MASK>0x10</EEPM0_MASK><EEPM1_MASK>0x20</EEPM1_MASK></EECR>
<PORTB>
<IO_ADDR>$18</IO_ADDR>
<MEM_ADDR>$38</MEM_ADDR>
<PORTB0_MASK>0x01</PORTB0_MASK><PORTB1_MASK>0x02</PORTB1_MASK><PORTB2_MASK>0x04</PORTB2_MASK><PORTB3_MASK>0x08</PORTB3_MASK><PORTB4_MASK>0x10</PORTB4_MASK><PORTB5_MASK>0x20</PORTB5_MASK></PORTB>
<DDRB>
<IO_ADDR>$17</IO_ADDR>
<MEM_ADDR>$37</MEM_ADDR>
<DDB0_MASK>0x01</DDB0_MASK><DDB1_MASK>0x02</DDB1_MASK><DDB2_MASK>0x04</DDB2_MASK><DDB3_MASK>0x08</DDB3_MASK><DDB4_MASK>0x10</DDB4_MASK><DDB5_MASK>0x20</DDB5_MASK></DDRB>
<PINB>
<IO_ADDR>$16</IO_ADDR>
<MEM_ADDR>$36</MEM_ADDR>
<PINB0_MASK>0x01</PINB0_MASK><PINB1_MASK>0x02</PINB1_MASK><PINB2_MASK>0x04</PINB2_MASK><PINB3_MASK>0x08</PINB3_MASK><PINB4_MASK>0x10</PINB4_MASK><PINB5_MASK>0x20</PINB5_MASK></PINB>
<PCMSK>
<IO_ADDR>$15</IO_ADDR>
<MEM_ADDR>$35</MEM_ADDR>
<PCINT0_MASK>0x01</PCINT0_MASK><PCINT1_MASK>0x02</PCINT1_MASK><PCINT2_MASK>0x04</PCINT2_MASK><PCINT3_MASK>0x08</PCINT3_MASK><PCINT4_MASK>0x10</PCINT4_MASK><PCINT5_MASK>0x20</PCINT5_MASK></PCMSK>
<DIDR0>
<IO_ADDR>$14</IO_ADDR>
<MEM_ADDR>$34</MEM_ADDR>
<AIN0D_MASK>0x01</AIN0D_MASK><AIN1D_MASK>0x02</AIN1D_MASK><ADC1D_MASK>0x04</ADC1D_MASK><ADC3D_MASK>0x08</ADC3D_MASK><ADC2D_MASK>0x10</ADC2D_MASK><ADC0D_MASK>0x20</ADC0D_MASK></DIDR0>
<GPIOR2>
<IO_ADDR>$13</IO_ADDR>
<MEM_ADDR>$33</MEM_ADDR>
<GPIOR20_MASK>0x01</GPIOR20_MASK><GPIOR21_MASK>0x02</GPIOR21_MASK><GPIOR22_MASK>0x04</GPIOR22_MASK><GPIOR23_MASK>0x08</GPIOR23_MASK><GPIOR24_MASK>0x10</GPIOR24_MASK><GPIOR25_MASK>0x20</GPIOR25_MASK><GPIOR26_MASK>0x40</GPIOR26_MASK><GPIOR27_MASK>0x80</GPIOR27_MASK></GPIOR2>
<GPIOR1>
<IO_ADDR>$12</IO_ADDR>
<MEM_ADDR>$32</MEM_ADDR>
<GPIOR10_MASK>0x01</GPIOR10_MASK><GPIOR11_MASK>0x02</GPIOR11_MASK><GPIOR12_MASK>0x04</GPIOR12_MASK><GPIOR13_MASK>0x08</GPIOR13_MASK><GPIOR14_MASK>0x10</GPIOR14_MASK><GPIOR15_MASK>0x20</GPIOR15_MASK><GPIOR16_MASK>0x40</GPIOR16_MASK><GPIOR17_MASK>0x80</GPIOR17_MASK></GPIOR1>
<GPIOR0>
<IO_ADDR>$11</IO_ADDR>
<MEM_ADDR>$31</MEM_ADDR>
<GPIOR00_MASK>0x01</GPIOR00_MASK><GPIOR01_MASK>0x02</GPIOR01_MASK><GPIOR02_MASK>0x04</GPIOR02_MASK><GPIOR03_MASK>0x08</GPIOR03_MASK><GPIOR04_MASK>0x10</GPIOR04_MASK><GPIOR05_MASK>0x20</GPIOR05_MASK><GPIOR06_MASK>0x40</GPIOR06_MASK><GPIOR07_MASK>0x80</GPIOR07_MASK></GPIOR0>
<USIBR>
<IO_ADDR>$10</IO_ADDR>
<MEM_ADDR>$30</MEM_ADDR>
<USIBR0_MASK>0x01</USIBR0_MASK><USIBR1_MASK>0x02</USIBR1_MASK><USIBR2_MASK>0x04</USIBR2_MASK><USIBR3_MASK>0x08</USIBR3_MASK><USIBR4_MASK>0x10</USIBR4_MASK><USIBR5_MASK>0x20</USIBR5_MASK><USIBR6_MASK>0x40</USIBR6_MASK><USIBR7_MASK>0x80</USIBR7_MASK></USIBR>
<USIDR>
<IO_ADDR>$0F</IO_ADDR>
<MEM_ADDR>$2F</MEM_ADDR>
<USIDR0_MASK>0x01</USIDR0_MASK><USIDR1_MASK>0x02</USIDR1_MASK><USIDR2_MASK>0x04</USIDR2_MASK><USIDR3_MASK>0x08</USIDR3_MASK><USIDR4_MASK>0x10</USIDR4_MASK><USIDR5_MASK>0x20</USIDR5_MASK><USIDR6_MASK>0x40</USIDR6_MASK><USIDR7_MASK>0x80</USIDR7_MASK></USIDR>
<USISR>
<IO_ADDR>$0E</IO_ADDR>
<MEM_ADDR>$2E</MEM_ADDR>
<USICNT0_MASK>0x01</USICNT0_MASK><USICNT1_MASK>0x02</USICNT1_MASK><USICNT2_MASK>0x04</USICNT2_MASK><USICNT3_MASK>0x08</USICNT3_MASK><USIDC_MASK>0x10</USIDC_MASK><USIPF_MASK>0x20</USIPF_MASK><USIOIF_MASK>0x40</USIOIF_MASK><USISIF_MASK>0x80</USISIF_MASK></USISR>
<USICR>
<IO_ADDR>$0D</IO_ADDR>
<MEM_ADDR>$2D</MEM_ADDR>
<USITC_MASK>0x01</USITC_MASK><USICLK_MASK>0x02</USICLK_MASK><USICS0_MASK>0x04</USICS0_MASK><USICS1_MASK>0x08</USICS1_MASK><USIWM0_MASK>0x10</USIWM0_MASK><USIWM1_MASK>0x20</USIWM1_MASK><USIOIE_MASK>0x40</USIOIE_MASK><USISIE_MASK>0x80</USISIE_MASK></USICR>
<ACSR>
<IO_ADDR>$08</IO_ADDR>
<MEM_ADDR>$28</MEM_ADDR>
<ACIS0_MASK>0x01</ACIS0_MASK><ACIS1_MASK>0x02</ACIS1_MASK><ACIE_MASK>0x08</ACIE_MASK><ACI_MASK>0x10</ACI_MASK><ACO_MASK>0x20</ACO_MASK><ACBG_MASK>0x40</ACBG_MASK><ACD_MASK>0x80</ACD_MASK></ACSR>
<ADMUX>
<IO_ADDR>$07</IO_ADDR>
<MEM_ADDR>$27</MEM_ADDR>
<MUX0_MASK>0x01</MUX0_MASK><MUX1_MASK>0x02</MUX1_MASK><MUX2_MASK>0x04</MUX2_MASK><MUX3_MASK>0x08</MUX3_MASK><REFS2_MASK>0x10</REFS2_MASK><ADLAR_MASK>0x20</ADLAR_MASK><REFS0_MASK>0x40</REFS0_MASK><REFS1_MASK>0x80</REFS1_MASK></ADMUX>
<ADCSRA>
<IO_ADDR>$06</IO_ADDR>
<MEM_ADDR>$26</MEM_ADDR>
<ADPS0_MASK>0x01</ADPS0_MASK><ADPS1_MASK>0x02</ADPS1_MASK><ADPS2_MASK>0x04</ADPS2_MASK><ADIE_MASK>0x08</ADIE_MASK><ADIF_MASK>0x10</ADIF_MASK><ADATE_MASK>0x20</ADATE_MASK><ADSC_MASK>0x40</ADSC_MASK><ADEN_MASK>0x80</ADEN_MASK></ADCSRA>
<ADCH>
<IO_ADDR>$05</IO_ADDR>
<MEM_ADDR>$25</MEM_ADDR>
<ADCH0_MASK>0x01</ADCH0_MASK><ADCH1_MASK>0x02</ADCH1_MASK><ADCH2_MASK>0x04</ADCH2_MASK><ADCH3_MASK>0x08</ADCH3_MASK><ADCH4_MASK>0x10</ADCH4_MASK><ADCH5_MASK>0x20</ADCH5_MASK><ADCH6_MASK>0x40</ADCH6_MASK><ADCH7_MASK>0x80</ADCH7_MASK></ADCH>
<ADCL>
<IO_ADDR>$04</IO_ADDR>
<MEM_ADDR>$24</MEM_ADDR>
<ADCL0_MASK>0x01</ADCL0_MASK><ADCL1_MASK>0x02</ADCL1_MASK><ADCL2_MASK>0x04</ADCL2_MASK><ADCL3_MASK>0x08</ADCL3_MASK><ADCL4_MASK>0x10</ADCL4_MASK><ADCL5_MASK>0x20</ADCL5_MASK><ADCL6_MASK>0x40</ADCL6_MASK><ADCL7_MASK>0x80</ADCL7_MASK></ADCL>
<ADCSRB>
<IO_ADDR>$03</IO_ADDR>
<MEM_ADDR>$23</MEM_ADDR>
<ACME_MASK>0x40</ACME_MASK><ADTS0_MASK>0x01</ADTS0_MASK><ADTS1_MASK>0x02</ADTS1_MASK><ADTS2_MASK>0x04</ADTS2_MASK><IPR_MASK>0x20</IPR_MASK><BIN_MASK>0x80</BIN_MASK></ADCSRB>
</IO_MEMORY>
<BOOT_CONFIG>
<NRWW_START_ADDR>$0</NRWW_START_ADDR>
<NRWW_STOP_ADDR>$7FF</NRWW_STOP_ADDR>
<RWW_START_ADDR>$0</RWW_START_ADDR>
<RWW_STOP_ADDR>$0</RWW_STOP_ADDR>
<PAGESIZE>32</PAGESIZE>
</BOOT_CONFIG>
</MEMORY>
<PACKAGE>
<PACKAGES>[PDIP:SOIC:MLF]</PACKAGES>
<DIP>
<NMB_PIN>8</NMB_PIN>
<PIN1>
<NAME>[PB5:'RESET:ADC0:PCINT5:dW]</NAME>
<TEXT/>
</PIN1>
<PIN2>
<NAME>[PB3:ADC3:'OC1B:XTAL1:PCINT4]</NAME>
<TEXT/>
</PIN2>
<PIN3>
<NAME>[PB4:ADC2:OC1B:XTAL2:PCINT3]</NAME>
<TEXT/>
</PIN3>
<PIN4>
<NAME>[GND]</NAME>
<TEXT/>
</PIN4>
<PIN5>
<NAME>[PB0:MOSI:DI:SDA:AIN0:OC0A:'OC1A:AREF:PCINT0]</NAME>
<TEXT/>
</PIN5>
<PIN6>
<NAME>[PB1:MISO:DO:AIN1:OC0B:OC1A:PCINT1]</NAME>
<TEXT/>
</PIN6>
<PIN7>
<NAME>[PB2:SCK:USCK:SCL:ADC1:T0:INT0:PCINT2]</NAME>
<TEXT/>
</PIN7>
<PIN8>
<NAME>[VCC]</NAME>
<TEXT/>
</PIN8>
</DIP>
</PACKAGE>
<INTERRUPT_VECTOR>
<NMB_VECTORS>15</NMB_VECTORS>
<VECTOR1>
<PROGRAM_ADDRESS>$000</PROGRAM_ADDRESS>
<SOURCE>RESET</SOURCE>
<DEFINITION>External Pin, Power-on Reset, Brown-out Reset,Watchdog Reset</DEFINITION>
</VECTOR1>
<VECTOR2>
<PROGRAM_ADDRESS>$001</PROGRAM_ADDRESS>
<SOURCE>INT0</SOURCE>
<DEFINITION>External Interrupt 0</DEFINITION>
</VECTOR2>
<VECTOR3>
<PROGRAM_ADDRESS>$002</PROGRAM_ADDRESS>
<SOURCE>PCINT0</SOURCE>
<DEFINITION>Pin change Interrupt Request 0</DEFINITION>
</VECTOR3>
<VECTOR4>
<PROGRAM_ADDRESS>$003</PROGRAM_ADDRESS>
<SOURCE>TIM1_COMPA</SOURCE>
<DEFINITION>Timer/Counter1 Compare Match 1A</DEFINITION>
</VECTOR4>
<VECTOR5>
<PROGRAM_ADDRESS>$004</PROGRAM_ADDRESS>
<SOURCE>TIM1_OVF</SOURCE>
<DEFINITION>Timer/Counter1 Overflow</DEFINITION>
</VECTOR5>
<VECTOR6>
<PROGRAM_ADDRESS>$005</PROGRAM_ADDRESS>
<SOURCE>TIM0_OVF</SOURCE>
<DEFINITION>Timer/Counter0 Overflow</DEFINITION>
</VECTOR6>
<VECTOR7>
<PROGRAM_ADDRESS>$006</PROGRAM_ADDRESS>
<SOURCE>EE_RDY</SOURCE>
<DEFINITION>EEPROM Ready</DEFINITION>
</VECTOR7>
<VECTOR8>
<PROGRAM_ADDRESS>$007</PROGRAM_ADDRESS>
<SOURCE>ANA_COMP</SOURCE>
<DEFINITION>Analog comparator</DEFINITION>
</VECTOR8>
<VECTOR9>
<PROGRAM_ADDRESS>$008</PROGRAM_ADDRESS>
<SOURCE>ADC</SOURCE>
<DEFINITION>ADC Conversion ready</DEFINITION>
</VECTOR9>
<VECTOR10>
<PROGRAM_ADDRESS>$009</PROGRAM_ADDRESS>
<SOURCE>TIM1_COMPB</SOURCE>
<DEFINITION>Timer/Counter1 Compare Match B</DEFINITION>
</VECTOR10>
<VECTOR11>
<PROGRAM_ADDRESS>$00A</PROGRAM_ADDRESS>
<SOURCE>TIM0_COMPA</SOURCE>
<DEFINITION>Timer/Counter0 Compare Match A</DEFINITION>
</VECTOR11>
<VECTOR12>
<PROGRAM_ADDRESS>$00B</PROGRAM_ADDRESS>
<SOURCE>TIM0_COMPB</SOURCE>
<DEFINITION>Timer/Counter0 Compare Match B</DEFINITION>
</VECTOR12>
<VECTOR13>
<PROGRAM_ADDRESS>$00C</PROGRAM_ADDRESS>
<SOURCE>WDT</SOURCE>
<DEFINITION>Watchdog Time-out</DEFINITION>
</VECTOR13>
<VECTOR14>
<PROGRAM_ADDRESS>$00D</PROGRAM_ADDRESS>
<SOURCE>USI_START</SOURCE>
<DEFINITION>USI START</DEFINITION>
</VECTOR14>
<VECTOR15>
<PROGRAM_ADDRESS>$00E</PROGRAM_ADDRESS>
<SOURCE>USI_OVF</SOURCE>
<DEFINITION>USI Overflow</DEFINITION>
</VECTOR15>
</INTERRUPT_VECTOR>
<FUSE>
<LIST>[LOW:HIGH:EXTENDED]</LIST>
<ICON/>
<ID/>
<TEXT/>
<LOW>
<NMB_TEXT>54</NMB_TEXT>
<NMB_FUSE_BITS>8</NMB_FUSE_BITS>
<TEXT1>
<MASK>0x80</MASK>
<VALUE>0x00</VALUE>
<TEXT>Divide clock by 8 internally; [CKDIV8=0]</TEXT>
</TEXT1>
<TEXT2>
<MASK>0x40</MASK>
<VALUE>0x00</VALUE>
<TEXT>Clock output on PORTB4; [CKOUT=0]</TEXT>
</TEXT2>
<TEXT3>
<MASK>0x3F</MASK>
<VALUE>0x00</VALUE>
<TEXT>Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms; [CKSEL=0000 SUT=00]</TEXT>
</TEXT3>
<TEXT4>
<MASK>0x3F</MASK>
<VALUE>0x10</VALUE>
<TEXT>Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms; [CKSEL=0000 SUT=01]</TEXT>
</TEXT4>
<TEXT5>
<MASK>0x3F</MASK>
<VALUE>0x20</VALUE>
<TEXT>Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms; [CKSEL=0000 SUT=10]</TEXT>
</TEXT5>
<TEXT6>
<MASK>0x3F</MASK>
<VALUE>0x01</VALUE>
<TEXT>PLL Clock; Start-up time PWRDWN/RESET: 1K CK/14 CK + 4 ms; [CKSEL=0001 SUT=00]</TEXT>
</TEXT6>
<TEXT7>
<MASK>0x3F</MASK>
<VALUE>0x11</VALUE>
<TEXT>PLL Clock; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4 ms; [CKSEL=0001 SUT=01]</TEXT>
</TEXT7>
<TEXT8>
<MASK>0x3F</MASK>
<VALUE>0x21</VALUE>
<TEXT>PLL Clock; Start-up time PWRDWN/RESET: 1K CK/14 CK + 64 ms; [CKSEL=0001 SUT=10]</TEXT>
</TEXT8>
<TEXT9>
<MASK>0x3F</MASK>
<VALUE>0x31</VALUE>
<TEXT>PLL Clock; Start-up time PWRDWN/RESET: 16K CK/14 CK + 64 ms; [CKSEL=0001 SUT=11]</TEXT>
</TEXT9>
<TEXT10>
<MASK>0x3F</MASK>
<VALUE>0x02</VALUE>
<TEXT>Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms; [CKSEL=0010 SUT=00]</TEXT>
</TEXT10>
<TEXT11>
<MASK>0x3F</MASK>
<VALUE>0x12</VALUE>
<TEXT>Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4 ms; [CKSEL=0010 SUT=01]</TEXT>
</TEXT11>
<TEXT12>
<MASK>0x3F</MASK>
<VALUE>0x22</VALUE>
<TEXT>Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 64 ms; [CKSEL=0010 SUT=10]; default value</TEXT>
</TEXT12>
<TEXT13>
<MASK>0x3F</MASK>
<VALUE>0x03</VALUE>
<TEXT>ATtiny15 Comp: Int. RC Osc. 6.4 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 64 ms; [CKSEL=0011 SUT=00]</TEXT>
</TEXT13>
<TEXT14>
<MASK>0x3F</MASK>
<VALUE>0x13</VALUE>
<TEXT>ATtiny15 Comp: Int. RC Osc. 6.4 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 64 ms; [CKSEL=0011 SUT=01]</TEXT>
</TEXT14>
<TEXT15>
<MASK>0x3F</MASK>
<VALUE>0x23</VALUE>
<TEXT>ATtiny15 Comp: Int. RC Osc. 6.4 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4 ms; [CKSEL=0011 SUT=10]</TEXT>
</TEXT15>
<TEXT16>
<MASK>0x3F</MASK>
<VALUE>0x33</VALUE>
<TEXT>ATtiny15 Comp: Int. RC Osc. 6.4 MHz; Start-up time PWRDWN/RESET: 1 CK/14 CK + 0 ms; [CKSEL=0011 SUT=11]</TEXT>
</TEXT16>
<TEXT17>
<MASK>0x3F</MASK>
<VALUE>0x04</VALUE>
<TEXT>WD. Osc. 128 kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms; [CKSEL=0100 SUT=00]</TEXT>
</TEXT17>
<TEXT18>
<MASK>0x3F</MASK>
<VALUE>0x14</VALUE>
<TEXT>WD. Osc. 128 kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4 ms; [CKSEL=0100 SUT=01]</TEXT>
</TEXT18>
<TEXT19>
<MASK>0x3F</MASK>
<VALUE>0x24</VALUE>
<TEXT>WD. Osc. 128 kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 64 ms; [CKSEL=0100 SUT=10]</TEXT>
</TEXT19>
<TEXT20>
<MASK>0x3F</MASK>
<VALUE>0x06</VALUE>
<TEXT>Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 0 ms; [CKSEL=0110 SUT=00] </TEXT>
</TEXT20>
<TEXT21>
<MASK>0x3F</MASK>
<VALUE>0x16</VALUE>
<TEXT>Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 4 ms; [CKSEL=0110 SUT=01] </TEXT>
</TEXT21>
<TEXT22>
<MASK>0x3F</MASK>
<VALUE>0x26</VALUE>
<TEXT>Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 64 ms; [CKSEL=0110 SUT=10] </TEXT>
</TEXT22>
<TEXT23>
<MASK>0x3F</MASK>
<VALUE>0x08</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms; [CKSEL=1000 SUT=00] </TEXT>
</TEXT23>
<TEXT24>
<MASK>0x3F</MASK>
<VALUE>0x18</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms; [CKSEL=1000 SUT=01] </TEXT>
</TEXT24>
<TEXT25>
<MASK>0x3F</MASK>
<VALUE>0x28</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms; [CKSEL=1000 SUT=10] </TEXT>
</TEXT25>
<TEXT26>
<MASK>0x3F</MASK>
<VALUE>0x38</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms; [CKSEL=1000 SUT=11] </TEXT>
</TEXT26>
<TEXT27>
<MASK>0x3F</MASK>
<VALUE>0x09</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms; [CKSEL=1001 SUT=00] </TEXT>
</TEXT27>
<TEXT28>
<MASK>0x3F</MASK>
<VALUE>0x19</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms; [CKSEL=1001 SUT=01] </TEXT>
</TEXT28>
<TEXT29>
<MASK>0x3F</MASK>
<VALUE>0x29</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms; [CKSEL=1001 SUT=10] </TEXT>
</TEXT29>
<TEXT30>
<MASK>0x3F</MASK>
<VALUE>0x39</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms; [CKSEL=1001 SUT=11] </TEXT>
</TEXT30>
<TEXT31>
<MASK>0x3F</MASK>
<VALUE>0x0A</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms; [CKSEL=1010 SUT=00] </TEXT>
</TEXT31>
<TEXT32>
<MASK>0x3F</MASK>
<VALUE>0x1A</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms; [CKSEL=1010 SUT=01] </TEXT>
</TEXT32>
<TEXT33>
<MASK>0x3F</MASK>
<VALUE>0x2A</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms; [CKSEL=1010 SUT=10] </TEXT>
</TEXT33>
<TEXT34>
<MASK>0x3F</MASK>
<VALUE>0x3A</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms; [CKSEL=1010 SUT=11] </TEXT>
</TEXT34>
<TEXT35>
<MASK>0x3F</MASK>
<VALUE>0x0B</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms; [CKSEL=1011 SUT=00] </TEXT>
</TEXT35>
<TEXT36>
<MASK>0x3F</MASK>
<VALUE>0x1B</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms; [CKSEL=1011 SUT=01] </TEXT>
</TEXT36>
<TEXT37>
<MASK>0x3F</MASK>
<VALUE>0x2B</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms; [CKSEL=1011 SUT=10] </TEXT>
</TEXT37>
<TEXT38>
<MASK>0x3F</MASK>
<VALUE>0x3B</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms; [CKSEL=1011 SUT=11] </TEXT>
</TEXT38>
<TEXT39>
<MASK>0x3F</MASK>
<VALUE>0x0C</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms; [CKSEL=1100 SUT=00] </TEXT>
</TEXT39>
<TEXT40>
<MASK>0x3F</MASK>
<VALUE>0x1C</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms; [CKSEL=1100 SUT=01] </TEXT>
</TEXT40>
<TEXT41>
<MASK>0x3F</MASK>
<VALUE>0x2C</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms; [CKSEL=1100 SUT=10] </TEXT>
</TEXT41>
<TEXT42>
<MASK>0x3F</MASK>
<VALUE>0x3C</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms; [CKSEL=1100 SUT=11] </TEXT>
</TEXT42>
<TEXT43>
<MASK>0x3F</MASK>
<VALUE>0x0D</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms; [CKSEL=1101 SUT=00] </TEXT>
</TEXT43>
<TEXT44>
<MASK>0x3F</MASK>
<VALUE>0x1D</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms; [CKSEL=1101 SUT=01] </TEXT>
</TEXT44>
<TEXT45>
<MASK>0x3F</MASK>
<VALUE>0x2D</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms; [CKSEL=1101 SUT=10] </TEXT>
</TEXT45>
<TEXT46>
<MASK>0x3F</MASK>
<VALUE>0x3D</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms; [CKSEL=1101 SUT=11] </TEXT>
</TEXT46>
<TEXT47>
<MASK>0x3F</MASK>
<VALUE>0x0E</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms; [CKSEL=1110 SUT=00] </TEXT>
</TEXT47>
<TEXT48>
<MASK>0x3F</MASK>
<VALUE>0x1E</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms; [CKSEL=1110 SUT=01] </TEXT>
</TEXT48>
<TEXT49>
<MASK>0x3F</MASK>
<VALUE>0x2E</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms; [CKSEL=1110 SUT=10] </TEXT>
</TEXT49>
<TEXT50>
<MASK>0x3F</MASK>
<VALUE>0x3E</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms; [CKSEL=1110 SUT=11] </TEXT>
</TEXT50>
<TEXT51>
<MASK>0x3F</MASK>
<VALUE>0x0F</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms; [CKSEL=1111 SUT=00] </TEXT>
</TEXT51>
<TEXT52>
<MASK>0x3F</MASK>
<VALUE>0x1F</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms; [CKSEL=1111 SUT=01] </TEXT>
</TEXT52>
<TEXT53>
<MASK>0x3F</MASK>
<VALUE>0x2F</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms; [CKSEL=1111 SUT=10] </TEXT>
</TEXT53>
<TEXT54>
<MASK>0x3F</MASK>
<VALUE>0x3F</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms; [CKSEL=1111 SUT=11] </TEXT>
</TEXT54>
<FUSE0>
<NAME>CKSEL0</NAME>
<TEXT>Select Clock source</TEXT>
<DEFAULT>0</DEFAULT>
</FUSE0>
<FUSE1>
<NAME>CKSEL1</NAME>
<TEXT>Select Clock source</TEXT>
<DEFAULT>1</DEFAULT>
</FUSE1>
<FUSE2>
<NAME>CKSEL2</NAME>
<TEXT>Select Clock source</TEXT>
<DEFAULT>0</DEFAULT>
</FUSE2>
<FUSE3>
<NAME>CKSEL3</NAME>
<TEXT>Select Clock source</TEXT>
<DEFAULT>1</DEFAULT>
</FUSE3>
<FUSE4>
<NAME>SUT0</NAME>
<TEXT>Select start-up time</TEXT>
<DEFAULT>0</DEFAULT>
</FUSE4>
<FUSE5>
<NAME>SUT1</NAME>
<TEXT>Select start-up time</TEXT>
<DEFAULT>1</DEFAULT>
</FUSE5>
<FUSE6>
<NAME>CKOUT</NAME>
<TEXT>Clock Output Enable</TEXT>
<DEFAULT>1</DEFAULT>
</FUSE6>
<FUSE7>
<NAME>CKDIV8</NAME>
<TEXT>Divide clock by 8</TEXT>
<DEFAULT>0</DEFAULT>
</FUSE7>
</LOW>
<HIGH>
<NMB_TEXT>9</NMB_TEXT>
<NMB_FUSE_BITS>8</NMB_FUSE_BITS>
<TEXT1>
<MASK>0x80</MASK>
<VALUE>0x00</VALUE>
<TEXT>Reset Disabled (Enable PB5 as i/o pin); [RSTDISBL=0]</TEXT>
</TEXT1>
<TEXT2>
<MASK>0x40</MASK>
<VALUE>0x00</VALUE>
<TEXT>Debug Wire enable; [DWEN=0]</TEXT>
</TEXT2>
<TEXT3>
<MASK>0x20</MASK>
<VALUE>0x00</VALUE>
<TEXT>Serial program downloading (SPI) enabled; [SPIEN=0]</TEXT>
</TEXT3>
<TEXT4>
<MASK>0x10</MASK>
<VALUE>0x00</VALUE>
<TEXT>Watch-dog Timer always on; [WDTON=0]</TEXT>
</TEXT4>
<TEXT5>
<MASK>0x08</MASK>
<VALUE>0x00</VALUE>
<TEXT>Preserve EEPROM memory through the Chip Erase cycle; [EESAVE=0]</TEXT>
</TEXT5>
<TEXT6>
<MASK>0x07</MASK>
<VALUE>0x04</VALUE>
<TEXT>Brown-out detection level at VCC=4.3 V; [BODLEVEL=100] </TEXT>
</TEXT6>
<TEXT7>
<MASK>0x07</MASK>
<VALUE>0x05</VALUE>
<TEXT>Brown-out detection level at VCC=2.7 V; [BODLEVEL=101] </TEXT>
</TEXT7>
<TEXT8>
<MASK>0x07</MASK>
<VALUE>0x06</VALUE>
<TEXT>Brown-out detection level at VCC=1.8 V; [BODLEVEL=110] </TEXT>
</TEXT8>
<TEXT9>
<MASK>0x07</MASK>
<VALUE>0x07</VALUE>
<TEXT>Brown-out detection disabled; [BODLEVEL=111] </TEXT>
</TEXT9>
<FUSE0>
<NAME>BODLEVEL0</NAME>
<TEXT>Brown-out Detector trigger level</TEXT>
<DEFAULT>1</DEFAULT>
</FUSE0>
<FUSE1>
<NAME>BODLEVEL1</NAME>
<TEXT>Brown-out Detector trigger level</TEXT>
<DEFAULT>1</DEFAULT>
</FUSE1>
<FUSE2>
<NAME>BODLEVEL2</NAME>
<TEXT>Brown-out Detector trigger level</TEXT>
<DEFAULT>1</DEFAULT>
</FUSE2>
<FUSE3>
<NAME>EESAVE</NAME>
<TEXT>EEPROM memory is preserved through the Chip Erase</TEXT>
<DEFAULT>1</DEFAULT>
</FUSE3>
<FUSE4>
<NAME>WDTON</NAME>
<TEXT>Watchdog Timer always on</TEXT>
<DEFAULT>1</DEFAULT>
</FUSE4>
<FUSE5>
<NAME>SPIEN</NAME>
<TEXT>Enable Serial Program and Data Downloading</TEXT>
<DEFAULT>0</DEFAULT>
</FUSE5>
<FUSE6>
<NAME>DWEN</NAME>
<TEXT>DebugWIRE Enable</TEXT>
<DEFAULT>1</DEFAULT>
</FUSE6>
<FUSE7>
<NAME>RSTDISBL</NAME>
<TEXT>External Reset disable</TEXT>
<DEFAULT>1</DEFAULT>
</FUSE7>
</HIGH>
<EXTENDED>
<FUSE0>
<NAME>SELFPRGEN</NAME>
<TEXT>Self-Programming Enable</TEXT>
<DEFAULT>1</DEFAULT>
</FUSE0>
<NMB_TEXT>1</NMB_TEXT>
<NMB_FUSE_BITS>1</NMB_FUSE_BITS>
<TEXT1>
<MASK>0x01</MASK>
<VALUE>0x00</VALUE>
<TEXT>Self Programming enable; [SELFPRGEN=0]</TEXT>
</TEXT1>
</EXTENDED>
</FUSE>
<FUSE>
<LIST/>
<ICON/>
<ID/>
<TEXT/>
<LOW>
<NMB_TEXT/>
<NMB_FUSE_BITS/>
<TEXT1>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT1>
<TEXT2>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT2>
<TEXT3>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT3>
<TEXT4>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT4>
<TEXT5>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT5>
<TEXT6>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT6>
<TEXT7>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT7>
<TEXT8>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT8>
<TEXT9>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT9>
<TEXT10>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT10>
<TEXT11>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT11>
<TEXT12>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT12>
<TEXT13>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT13>
<TEXT14>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT14>
<TEXT15>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT15>
<TEXT16>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT16>
<TEXT17>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT17>
<TEXT18>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT18>
<TEXT19>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT19>
<TEXT20>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT20>
<TEXT21>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT21>
<TEXT22>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT22>
<TEXT23>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT23>
<TEXT24>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT24>
<TEXT25>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT25>
<TEXT26>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT26>
<TEXT27>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT27>
<TEXT28>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT28>
<TEXT29>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT29>
<TEXT30>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT30>
<TEXT31>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT31>
<TEXT32>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT32>
<TEXT33>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT33>
<TEXT34>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT34>
<TEXT35>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT35>
<TEXT36>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT36>
<TEXT37>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT37>
<TEXT38>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT38>
<TEXT39>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT39>
<TEXT40>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT40>
<TEXT41>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT41>
<TEXT42>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT42>
<TEXT43>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT43>
<TEXT44>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT44>
<TEXT45>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT45>
<TEXT46>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT46>
<TEXT47>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT47>
<TEXT48>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT48>
<TEXT49>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT49>
<TEXT50>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT50>
<TEXT51>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT51>
<TEXT52>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT52>
<TEXT53>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT53>
<TEXT54>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT54>
<FUSE0>
<NAME/>
<TEXT/>
<DEFAULT/>
</FUSE0>
<FUSE1>
<NAME/>
<TEXT/>
<DEFAULT/>
</FUSE1>
<FUSE2>
<NAME/>
<TEXT/>
<DEFAULT/>
</FUSE2>
<FUSE3>
<NAME/>
<TEXT/>
<DEFAULT/>
</FUSE3>
<FUSE4>
<NAME/>
<TEXT/>
<DEFAULT/>
</FUSE4>
<FUSE5>
<NAME/>
<TEXT/>
<DEFAULT/>
</FUSE5>
<FUSE6>
<NAME/>
<TEXT/>
<DEFAULT/>
</FUSE6>
<FUSE7>
<NAME/>
<TEXT/>
<DEFAULT/>
</FUSE7>
</LOW>
<HIGH>
<NMB_TEXT/>
<NMB_FUSE_BITS/>
<TEXT1>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT1>
<TEXT2>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT2>
<TEXT3>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT3>
<TEXT4>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT4>
<TEXT5>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT5>
<TEXT6>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT6>
<TEXT7>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT7>
<TEXT8>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT8>
<TEXT9>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT9>
<FUSE0>
<NAME/>
<TEXT/>
<DEFAULT/>
</FUSE0>
<FUSE1>
<NAME/>
<TEXT/>
<DEFAULT/>
</FUSE1>
<FUSE2>
<NAME/>
<TEXT/>
<DEFAULT/>
</FUSE2>
<FUSE3>
<NAME/>
<TEXT/>
<DEFAULT/>
</FUSE3>
<FUSE4>
<NAME/>
<TEXT/>
<DEFAULT/>
</FUSE4>
<FUSE5>
<NAME/>
<TEXT/>
<DEFAULT/>
</FUSE5>
<FUSE6>
<NAME/>
<TEXT/>
<DEFAULT/>
</FUSE6>
<FUSE7>
<NAME/>
<TEXT/>
<DEFAULT/>
</FUSE7>
</HIGH>
<EXTENDED>
<FUSE0>
<NAME/>
<TEXT/>
<DEFAULT/>
</FUSE0>
<NMB_TEXT/>
<NMB_FUSE_BITS/>
<TEXT1>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT1>
</EXTENDED>
</FUSE>
<FUSE>
<LIST/>
<ICON/>
<ID/>
<TEXT/>
<LOW>
<NMB_TEXT/>
<NMB_FUSE_BITS/>
<TEXT1>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT1>
<TEXT2>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT2>
<TEXT3>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT3>
<TEXT4>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT4>
<TEXT5>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT5>
<TEXT6>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT6>
<TEXT7>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT7>
<TEXT8>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT8>
<TEXT9>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT9>
<TEXT10>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT10>
<TEXT11>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT11>
<TEXT12>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT12>
<TEXT13>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT13>
<TEXT14>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT14>
<TEXT15>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT15>
<TEXT16>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT16>
<TEXT17>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT17>
<TEXT18>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT18>
<TEXT19>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT19>
<TEXT20>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT20>
<TEXT21>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT21>
<TEXT22>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT22>
<TEXT23>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT23>
<TEXT24>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT24>
<TEXT25>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT25>
<TEXT26>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT26>
<TEXT27>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT27>
<TEXT28>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT28>
<TEXT29>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT29>
<TEXT30>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT30>
<TEXT31>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT31>
<TEXT32>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT32>
<TEXT33>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT33>
<TEXT34>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT34>
<TEXT35>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT35>
<TEXT36>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT36>
<TEXT37>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT37>
<TEXT38>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT38>
<TEXT39>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT39>
<TEXT40>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT40>
<TEXT41>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT41>
<TEXT42>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT42>
<TEXT43>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT43>
<TEXT44>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT44>
<TEXT45>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT45>
<TEXT46>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT46>
<TEXT47>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT47>
<TEXT48>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT48>
<TEXT49>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT49>
<TEXT50>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT50>
<TEXT51>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT51>
<TEXT52>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT52>
<TEXT53>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT53>
<TEXT54>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT54>
<FUSE0>
<NAME/>
<TEXT/>
<DEFAULT/>
</FUSE0>
<FUSE1>
<NAME/>
<TEXT/>
<DEFAULT/>
</FUSE1>
<FUSE2>
<NAME/>
<TEXT/>
<DEFAULT/>
</FUSE2>
<FUSE3>
<NAME/>
<TEXT/>
<DEFAULT/>
</FUSE3>
<FUSE4>
<NAME/>
<TEXT/>
<DEFAULT/>
</FUSE4>
<FUSE5>
<NAME/>
<TEXT/>
<DEFAULT/>
</FUSE5>
<FUSE6>
<NAME/>
<TEXT/>
<DEFAULT/>
</FUSE6>
<FUSE7>
<NAME/>
<TEXT/>
<DEFAULT/>
</FUSE7>
</LOW>
<HIGH>
<NMB_TEXT/>
<NMB_FUSE_BITS/>
<TEXT1>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT1>
<TEXT2>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT2>
<TEXT3>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT3>
<TEXT4>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT4>
<TEXT5>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT5>
<TEXT6>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT6>
<TEXT7>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT7>
<TEXT8>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT8>
<TEXT9>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT9>
<FUSE0>
<NAME/>
<TEXT/>
<DEFAULT/>
</FUSE0>
<FUSE1>
<NAME/>
<TEXT/>
<DEFAULT/>
</FUSE1>
<FUSE2>
<NAME/>
<TEXT/>
<DEFAULT/>
</FUSE2>
<FUSE3>
<NAME/>
<TEXT/>
<DEFAULT/>
</FUSE3>
<FUSE4>
<NAME/>
<TEXT/>
<DEFAULT/>
</FUSE4>
<FUSE5>
<NAME/>
<TEXT/>
<DEFAULT/>
</FUSE5>
<FUSE6>
<NAME/>
<TEXT/>
<DEFAULT/>
</FUSE6>
<FUSE7>
<NAME/>
<TEXT/>
<DEFAULT/>
</FUSE7>
</HIGH>
<EXTENDED>
<FUSE0>
<NAME/>
<TEXT/>
<DEFAULT/>
</FUSE0>
<NMB_TEXT/>
<NMB_FUSE_BITS/>
<TEXT1>
<MASK/>
<VALUE/>
<TEXT/>
</TEXT1>
</EXTENDED>
</FUSE>
<PROGRAMMING>
<ISPInterface>
<FuseReadMask>0xff,0xdf, 0x01</FuseReadMask>
<FuseProgMask>0xff,0xdf, 0x01</FuseProgMask>
<FuseWarning>1,0x20,0x20,WARNING! These fuse settings will disable the ISP interface!</FuseWarning>
<FuseWarning>1,0x40,0x00,WARNING! Enabling DEBUGWIRE will make the ISP interface inaccessible!</FuseWarning>
<FuseWarning>1,0x80,0x00,WARNING! Disabling external reset will make the ISP interface inaccessible!</FuseWarning>
</ISPInterface>
<HVInterface>
<FuseWarning>1,0x20,0x20,WARNING! These fuse settings will disable the ISP interface!</FuseWarning>
<FuseWarning>1,0x40,0x00,WARNING! Enabling DEBUGWIRE will make the ISP interface inaccessible!</FuseWarning>
<FuseWarning>1,0x80,0x00,WARNING! Disabling external reset will make the ISP interface inaccessible!</FuseWarning>
</HVInterface>
<OscCal>
<OCEntry>0x00,8.0 MHz</OCEntry>
<OCEntry>0x01,6.4 MHz</OCEntry>
</OscCal>
<FlashPageSize>64</FlashPageSize>
<EepromPageSize>4</EepromPageSize>
</PROGRAMMING>
<LOCKBIT>
<ICON/>
<ID/>
<TEXT>[LB1 = 1 : LB2 = 1] No memory lock features enabled. [LB1 = 0 : LB2 = 1] Further programming of Flash and EEPROM is enabled. [LB1 = 0 : LB2 = 0] Same as previous, but verify is also disabled</TEXT>
<NMB_TEXT>3</NMB_TEXT>
<NMB_LOCK_BITS>2</NMB_LOCK_BITS>
<TEXT1>
<MASK>0x03</MASK>
<VALUE>0x03</VALUE>
<TEXT>Mode 1: No memory lock features enabled</TEXT>
</TEXT1>
<TEXT2>
<MASK>0x03</MASK>
<VALUE>0x02</VALUE>
<TEXT>Mode 2: Further programming disabled</TEXT>
</TEXT2>
<TEXT3>
<MASK>0x03</MASK>
<VALUE>0x00</VALUE>
<TEXT>Mode 3: Further programming and verification disabled</TEXT>
</TEXT3>
<LOCKBIT0>
<NAME>LB1</NAME>
<TEXT>Lockbit</TEXT>
</LOCKBIT0>
<LOCKBIT1>
<NAME>LB2</NAME>
<TEXT>Lockbit</TEXT>
</LOCKBIT1>
</LOCKBIT>
<IO_MODULE><MODULE_LIST>[PORTB:ANALOG_COMPARATOR:AD_CONVERTER:USI:EXTERNAL_INTERRUPT:EEPROM:WATCHDOG:TIMER_COUNTER_0:TIMER_COUNTER_1:CPU:BOOT_LOAD]</MODULE_LIST><PORTB>
<LIST>[PORTB:DDRB:PINB]</LIST>
<LINK/>
<ICON>io_port.bmp</ICON>
<ID>AVRSimIOPort.SimIOPort</ID>
<TEXT/>
<PORTB>
<NAME>PORTB</NAME>
<DESCRIPTION>Data Register, Port B</DESCRIPTION>
<TEXT/>
<IO_ADDR>$18</IO_ADDR>
<MEM_ADDR>$38</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT5>
<NAME>PORTB5</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PORTB4</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PORTB3</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PORTB2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PORTB1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PORTB0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PORTB>
<DDRB>
<NAME>DDRB</NAME>
<DESCRIPTION>Data Direction Register, Port B</DESCRIPTION>
<TEXT/>
<IO_ADDR>$17</IO_ADDR>
<MEM_ADDR>$37</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT5>
<NAME>DDB5</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>DDB4</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>DDB3</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>DDB2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>DDB1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>DDB0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</DDRB>
<PINB>
<NAME>PINB</NAME>
<DESCRIPTION>Input Pins, Port B</DESCRIPTION>
<TEXT/>
<IO_ADDR>$16</IO_ADDR>
<MEM_ADDR>$36</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT5>
<NAME>PINB5</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PINB4</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PINB3</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PINB2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PINB1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PINB0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PINB>
</PORTB>
<ANALOG_COMPARATOR>
<LIST>[ADCSRB:ACSR:DIDR0]</LIST>
<LINK/>
<ICON>io_analo.bmp</ICON>
<ID>AlgComp_01</ID>
<TEXT/>
<ADCSRB>
<NAME>ADCSRB</NAME>
<DESCRIPTION>ADC Control and Status Register B</DESCRIPTION>
<TEXT/>
<IO_ADDR>$03</IO_ADDR>
<MEM_ADDR>$23</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT6>
<NAME>ACME</NAME>
<DESCRIPTION>Analog Comparator Multiplexer Enable</DESCRIPTION>
<TEXT>When this bit is written logic one and the ADC is switched off (ADEN in ADCSR is zero), the ADC multiplexer selects the negative input to the Analog Comparator. When this bit is written logic zero, AIN1 is applied to the negative input of the Analog Comparator. For a detailed description of this bit, see “Analog Comparator Multiplexed Input” on page 186.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
</ADCSRB>
<ACSR>
<NAME>ACSR</NAME>
<DESCRIPTION>Analog Comparator Control And Status Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$08</IO_ADDR>
<MEM_ADDR>$28</MEM_ADDR>
<ICON>io_analo.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>ACD</NAME>
<DESCRIPTION>Analog Comparator Disable</DESCRIPTION>
<TEXT>When this bit is written logic one, the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>ACBG</NAME>
<ALIAS>AINBG</ALIAS>
<DESCRIPTION>Analog Comparator Bandgap Select</DESCRIPTION>
<TEXT>When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. See “Internal Voltage Reference” on page 42.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>ACO</NAME>
<DESCRIPTION>Analog Compare Output</DESCRIPTION>
<TEXT>The output of the analog comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1-2 clock cycles.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>NA</INIT_VAL>
</BIT5>
<BIT4>
<NAME>ACI</NAME>
<DESCRIPTION>Analog Comparator Interrupt Flag</DESCRIPTION>
<TEXT>This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hard-ware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>ACIE</NAME>
<DESCRIPTION>Analog Comparator Interrupt Enable</DESCRIPTION>
<TEXT>When the ACIE bit is written logic one and the I-bit in the Status Register is set, the analog comparator interrupt is acti-vated. When written logic zero, the interrupt is disabled.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT1>
<NAME>ACIS1</NAME>
<DESCRIPTION>Analog Comparator Interrupt Mode Select bit 1</DESCRIPTION>
<TEXT>These bits determine which comparator events that trigger the Analog Comparator interrupt.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>ACIS0</NAME>
<DESCRIPTION>Analog Comparator Interrupt Mode Select bit 0</DESCRIPTION>
<TEXT>These bits determine which comparator events that trigger the Analog Comparator interrupt.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</ACSR>
<DIDR0>
<NAME>DIDR0</NAME>
<DESCRIPTION/>
<TEXT/>
<IO_ADDR>$14</IO_ADDR>
<MEM_ADDR>$34</MEM_ADDR>
<ICON/>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT1>
<NAME>AIN1D</NAME>
<DESCRIPTION>AIN1 Digital Input Disable</DESCRIPTION>
<TEXT>When this bit is written logic one,the digital input buffer on the AIN1/0 pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the AIN1/0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>AIN0D</NAME>
<DESCRIPTION>AIN0 Digital Input Disable</DESCRIPTION>
<TEXT>When this bit is written logic one,the digital input buffer on the AIN1/0 pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the AIN1/0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</DIDR0>
</ANALOG_COMPARATOR>
<AD_CONVERTER>
<LIST>[ADMUX:ADCSRA:ADCH:ADCL:ADCSRB:DIDR0]</LIST>
<LINK/>
<RULES>((IF ADMUX.ADLAR = 1) LINK [ADCH(1:0):ADCL(7:0)]); (IF ADMUX.ADLAR = 0) LINK [ADCH(7:0):ADCL(7:6)]);</RULES>
<ICON>io_analo.bmp</ICON>
<ID/>
<TEXT>AD Converter Feature list: 10-bit Resolution. 0.5 LSB Integral Non-Linearity. +-2 LSB Absolute Accuracy. TBD - 260 µs Conversion Time. Up to TBD kSPS at maximum resolution. 8 Multiplexed Single Ended Input Channels. 7 Differential input channels (TQFP package only). 2 Differential input channels with optional gain of 10x and 200x (TQFP package only). Optional left adjustment for ADC result readout. 0 - VCC ADC Input Voltage Range. Selectable 2.56 V ADC reference voltage. Free Running or Single Conversion Mode. Interrupt on ADC Conversion Complete. Sleep Mode N</TEXT>
<ADMUX>
<NAME>ADMUX</NAME>
<DESCRIPTION>The ADC multiplexer Selection Register</DESCRIPTION>
<TEXT>These bits select the voltage reference for the ADC, as shown in Table 91. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin.</TEXT>
<IO_ADDR>$07</IO_ADDR>
<MEM_ADDR>$27</MEM_ADDR>
<ICON>io_analo.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>REFS1</NAME>
<DESCRIPTION>Reference Selection Bit 1</DESCRIPTION>
<TEXT>These bits select the voltage reference for the ADC. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>REFS0</NAME>
<DESCRIPTION>Reference Selection Bit 0</DESCRIPTION>
<TEXT>These bits select the voltage reference for the ADC. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>ADLAR</NAME>
<DESCRIPTION>Left Adjust Result</DESCRIPTION>
<TEXT>The ADLAR bit affects the presentation of the ADC conversion result in the ADC data register. If ADLAR is cleared, the result is right adjusted. If ADLAR is set, the result is left adjusted. Changing the ADLAR bit will affect the ADC data register immediately, regardless of any ongoing conversions. For a complete description of this bit, see “The ADC Data Register -ADCL and ADCH” on page 198. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>REFS2</NAME>
<DESCRIPTION>Reference Selection Bit 2</DESCRIPTION>
<TEXT>These bits select the voltage reference for the ADC. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>MUX3</NAME>
<DESCRIPTION>Analog Channel and Gain Selection Bits</DESCRIPTION>
<TEXT>The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>MUX2</NAME>
<DESCRIPTION>Analog Channel and Gain Selection Bits</DESCRIPTION>
<TEXT>The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>MUX1</NAME>
<DESCRIPTION>Analog Channel and Gain Selection Bits</DESCRIPTION>
<TEXT>The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>MUX0</NAME>
<DESCRIPTION>Analog Channel and Gain Selection Bits</DESCRIPTION>
<TEXT>The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</ADMUX>
<ADCSRA>
<NAME>ADCSRA</NAME>
<DESCRIPTION>The ADC Control and Status register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$06</IO_ADDR>
<MEM_ADDR>$26</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>ADEN</NAME>
<DESCRIPTION>ADC Enable</DESCRIPTION>
<TEXT>Writing a logical ‘1’ to this bit enables the ADC. By clearing this bit to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>ADSC</NAME>
<DESCRIPTION>ADC Start Conversion</DESCRIPTION>
<TEXT>In Single Conversion Mode, a logical ‘1’ must be written to this bit to start each conversion. In Free Running Mode, a logical ‘1’ must be written to this bit to start the first conversion. The first time ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, an extended conversion will result. This extended conversion performs initialization of the ADC. ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. When a dummy conversion precedes a real conversion, ADSC will stay high until the real conversion completes. Writing a 0 to this bit has no effect</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>ADATE</NAME>
<DESCRIPTION>ADC Auto Trigger Enable</DESCRIPTION>
<TEXT>When this bit is written to one,Auto Triggering of the ADC is enabled.The ADC will start a conversion on a positive edge of the selected trigger signal.The trigger source is selected by setting the ADC Trigger Select bits,ADTS in ADCSRB. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>ADIF</NAME>
<DESCRIPTION>ADC Interrupt Flag</DESCRIPTION>
<TEXT>This bit is set (one) when an ADC conversion completes and the data registers are updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set (one). ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a read-modify-write on ADCSR, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>ADIE</NAME>
<DESCRIPTION>ADC Interrupt Enable</DESCRIPTION>
<TEXT>When this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Complete Interrupt is activated.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>ADPS2</NAME>
<DESCRIPTION>ADC Prescaler Select Bits</DESCRIPTION>
<TEXT>These bits determine the division factor between the XTAL frequency and the input clock to the ADC.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>ADPS1</NAME>
<DESCRIPTION>ADC Prescaler Select Bits</DESCRIPTION>
<TEXT>These bits determine the division factor between the XTAL frequency and the input clock to the ADC.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>ADPS0</NAME>
<DESCRIPTION>ADC Prescaler Select Bits</DESCRIPTION>
<TEXT>These bits determine the division factor between the XTAL frequency and the input clock to the ADC.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</ADCSRA>
<ADCH>
<NAME>ADCH</NAME>
<DESCRIPTION>ADC Data Register High Byte</DESCRIPTION>
<TEXT>When an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form. The selected channel is differential if MUX4..0 are between ‘01000’ and ‘11101’, otherwise the selected channel is single ended. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8 bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUX4..0 bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right </TEXT>
<IO_ADDR>$05</IO_ADDR>
<MEM_ADDR>$25</MEM_ADDR>
<ICON>io_analo.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>ADCH7</NAME>
<DESCRIPTION>ADC Data Register High Byte Bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>ADCH6</NAME>
<DESCRIPTION>ADC Data Register High Byte Bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>ADCH5</NAME>
<DESCRIPTION>ADC Data Register High Byte Bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>ADCH4</NAME>
<DESCRIPTION>ADC Data Register High Byte Bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>ADCH3</NAME>
<DESCRIPTION>ADC Data Register High Byte Bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>ADCH2</NAME>
<DESCRIPTION>ADC Data Register High Byte Bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>ADCH1</NAME>
<DESCRIPTION>ADC Data Register High Byte Bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>ADCH0</NAME>
<DESCRIPTION>ADC Data Register High Byte Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</ADCH>
<ADCL>
<NAME>ADCL</NAME>
<DESCRIPTION>ADC Data Register Low Byte</DESCRIPTION>
<TEXT>When an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form. The selected channel is differential if MUX4..0 are between ‘01000’ and ‘11101’, otherwise the selected channel is single ended. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8 bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUX4..0 bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right</TEXT>
<IO_ADDR>$04</IO_ADDR>
<MEM_ADDR>$24</MEM_ADDR>
<ICON>io_analo.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>ADCL7</NAME>
<DESCRIPTION>ADC Data Register Low Byte Bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>ADCL6</NAME>
<DESCRIPTION>ADC Data Register Low Byte Bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>ADCL5</NAME>
<DESCRIPTION>ADC Data Register Low Byte Bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>ADCL4</NAME>
<DESCRIPTION>ADC Data Register Low Byte Bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>ADCL3</NAME>
<DESCRIPTION>ADC Data Register Low Byte Bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>ADCL2</NAME>
<DESCRIPTION>ADC Data Register Low Byte Bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>ADCL1</NAME>
<DESCRIPTION>ADC Data Register Low Byte Bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>ADCL0</NAME>
<DESCRIPTION>ADC Data Register Low Byte Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</ADCL>
<ADCSRB>
<NAME>ADCSRB</NAME>
<DESCRIPTION>ADC Control and Status Register B</DESCRIPTION>
<TEXT/>
<IO_ADDR>$03</IO_ADDR>
<MEM_ADDR>$23</MEM_ADDR>
<ICON>io_analo.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>BIN</NAME>
<DESCRIPTION>Bipolar Input Mode</DESCRIPTION>
<TEXT>The gain stage is working in the unipolar mode as default, but the bipolar mode can be selected by writing the BIN bit in the ADCSRB register.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT5>
<NAME>IPR</NAME>
<DESCRIPTION>Input Polarity Mode</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT2>
<NAME>ADTS2</NAME>
<DESCRIPTION>ADC Auto Trigger Source 2</DESCRIPTION>
<TEXT>If ADATE in ADCSRA is written to one,the value of these bits selects which source will trigger an ADC conversion.If ADATE is cleared,the ADTS2:0 settings will have no effect.A conversion will be triggered by the rising edge of the selected interrupt flag.Note that switching from a trigger source that is cleared to a trigger source that is set,will generate a positive edge on the trigger signal.If ADEN in ADCSRA is set,this will start a conversion.Switching to Free Running Mode (ADTS [2:0 ]=0)will not cause a trigger event,even if the ADC Interrupt Flag is set . </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>ADTS1</NAME>
<DESCRIPTION>ADC Auto Trigger Source 1</DESCRIPTION>
<TEXT>If ADATE in ADCSRA is written to one,the value of these bits selects which source will trigger an ADC conversion.If ADATE is cleared,the ADTS2:0 settings will have no effect.A conversion will be triggered by the rising edge of the selected interrupt flag.Note that switching from a trigger source that is cleared to a trigger source that is set,will generate a positive edge on the trigger signal.If ADEN in ADCSRA is set,this will start a conversion.Switching to Free Running Mode (ADTS [2:0 ]=0)will not cause a trigger event,even if the ADC Interrupt Flag is set . </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>ADTS0</NAME>
<DESCRIPTION>ADC Auto Trigger Source 0</DESCRIPTION>
<TEXT>If ADATE in ADCSRA is written to one,the value of these bits selects which source will trigger an ADC conversion.If ADATE is cleared,the ADTS2:0 settings will have no effect.A conversion will be triggered by the rising edge of the selected interrupt flag.Note that switching from a trigger source that is cleared to a trigger source that is set,will generate a positive edge on the trigger signal.If ADEN in ADCSRA is set,this will start a conversion.Switching to Free Running Mode (ADTS [2:0 ]=0)will not cause a trigger event,even if the ADC Interrupt Flag is set . </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</ADCSRB>
<DIDR0>
<NAME>DIDR0</NAME>
<DESCRIPTION>Digital Input Disable Register 0</DESCRIPTION>
<TEXT/>
<IO_ADDR>$14</IO_ADDR>
<MEM_ADDR>$34</MEM_ADDR>
<ICON>io_analo.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT5>
<NAME>ADC0D</NAME>
<DESCRIPTION>ADC0 Digital input Disable</DESCRIPTION>
<TEXT>When this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. </TEXT>
<ACCESS/>
<INIT_VAL/>
</BIT5>
<BIT4>
<NAME>ADC2D</NAME>
<DESCRIPTION>ADC2 Digital input Disable</DESCRIPTION>
<TEXT>When this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. </TEXT>
<ACCESS/>
<INIT_VAL/>
</BIT4>
<BIT3>
<NAME>ADC3D</NAME>
<DESCRIPTION>ADC3 Digital input Disable</DESCRIPTION>
<TEXT>When this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. </TEXT>
<ACCESS/>
<INIT_VAL/>
</BIT3>
<BIT2>
<NAME>ADC1D</NAME>
<DESCRIPTION>ADC1 Digital input Disable</DESCRIPTION>
<TEXT>When this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. </TEXT>
<ACCESS/>
<INIT_VAL/>
</BIT2>
</DIDR0>
</AD_CONVERTER>
<USI>
<LIST>[USIBR:USIDR:USISR:USICR]</LIST>
<LINK/>
<ICON>io_com.bmp</ICON>
<ID/>
<TEXT>Universal Serial Interface</TEXT>
<USIBR>
<NAME>USIBR</NAME>
<DESCRIPTION>USI Buffer Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$10</IO_ADDR>
<MEM_ADDR>$30</MEM_ADDR>
<ICON>io_com.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>USIBR7</NAME>
<DESCRIPTION>USI Buffer Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>USIBR6</NAME>
<DESCRIPTION>USI Buffer Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>USIBR5</NAME>
<DESCRIPTION>USI Buffer Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>USIBR4</NAME>
<DESCRIPTION>USI Buffer Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>USIBR3</NAME>
<DESCRIPTION>USI Buffer Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>USIBR2</NAME>
<DESCRIPTION>USI Buffer Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>USIBR1</NAME>
<DESCRIPTION>USI Buffer Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>USIBR0</NAME>
<DESCRIPTION>USI Buffer Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</USIBR>
<USIDR>
<NAME>USIDR</NAME>
<DESCRIPTION>USI Data Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$0F</IO_ADDR>
<MEM_ADDR>$2F</MEM_ADDR>
<ICON>io_com.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>USIDR7</NAME>
<DESCRIPTION>USI Data Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>USIDR6</NAME>
<DESCRIPTION>USI Data Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>USIDR5</NAME>
<DESCRIPTION>USI Data Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>USIDR4</NAME>
<DESCRIPTION>USI Data Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>USIDR3</NAME>
<DESCRIPTION>USI Data Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>USIDR2</NAME>
<DESCRIPTION>USI Data Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>USIDR1</NAME>
<DESCRIPTION>USI Data Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>USIDR0</NAME>
<DESCRIPTION>USI Data Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</USIDR>
<USISR>
<NAME>USISR</NAME>
<DESCRIPTION>USI Status Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$0E</IO_ADDR>
<MEM_ADDR>$2E</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>USISIF</NAME>
<DESCRIPTION>Start Condition Interrupt Flag</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>USIOIF</NAME>
<DESCRIPTION>Counter Overflow Interrupt Flag</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>USIPF</NAME>
<DESCRIPTION>Stop Condition Flag</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT5>
<BIT4>
<NAME>USIDC</NAME>
<DESCRIPTION>Data Output Collision</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>USICNT3</NAME>
<DESCRIPTION>USI Counter Value Bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>USICNT2</NAME>
<DESCRIPTION>USI Counter Value Bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>USICNT1</NAME>
<DESCRIPTION>USI Counter Value Bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>USICNT0</NAME>
<DESCRIPTION>USI Counter Value Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</USISR>
<USICR>
<NAME>USICR</NAME>
<DESCRIPTION>USI Control Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$0D</IO_ADDR>
<MEM_ADDR>$2D</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>USISIE</NAME>
<DESCRIPTION>Start Condition Interrupt Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>USIOIE</NAME>
<DESCRIPTION>Counter Overflow Interrupt Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>USIWM1</NAME>
<DESCRIPTION>USI Wire Mode Bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT5>
<BIT4>
<NAME>USIWM0</NAME>
<DESCRIPTION>USI Wire Mode Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>USICS1</NAME>
<DESCRIPTION>USI Clock Source Select Bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>USICS0</NAME>
<DESCRIPTION>USI Clock Source Select Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>USICLK</NAME>
<DESCRIPTION>Clock Strobe</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>USITC</NAME>
<DESCRIPTION>Toggle Clock Port Pin</DESCRIPTION>
<TEXT/>
<ACCESS>W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</USICR>
</USI>
<EXTERNAL_INTERRUPT>
<LIST>[MCUCR:GIMSK:GIFR:PCMSK]</LIST>
<LINK/>
<ICON>io_ext.bmp</ICON>
<ID/>
<TEXT/>
<MCUCR>
<NAME>MCUCR</NAME>
<DESCRIPTION>MCU Control Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$35</IO_ADDR>
<MEM_ADDR>$55</MEM_ADDR>
<ICON>io_cpu.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT1>
<NAME>ISC01</NAME>
<DESCRIPTION>Interrupt Sense Control 0 Bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>ISC00</NAME>
<DESCRIPTION>Interrupt Sense Control 0 Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</MCUCR>
<GIMSK>
<NAME>GIMSK</NAME>
<ALIAS>GICR</ALIAS>
<DESCRIPTION>General Interrupt Mask Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$3B</IO_ADDR>
<MEM_ADDR>$5B</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT6>
<NAME>INT0</NAME>
<DESCRIPTION>External Interrupt Request 0 Enable</DESCRIPTION>
<TEXT>When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU general Control Register (MCUCR) defines whether the external interrupt is activated on rising or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from program memory address $001. See also “External Interrupts.” • Bits 5..0 - Res: Reserved bits</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PCIE</NAME>
<DESCRIPTION>Pin Change Interrupt Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
</GIMSK>
<GIFR>
<NAME>GIFR</NAME>
<DESCRIPTION>General Interrupt Flag register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$3A</IO_ADDR>
<MEM_ADDR>$5A</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT6>
<NAME>INTF0</NAME>
<DESCRIPTION>External Interrupt Flag 0</DESCRIPTION>
<TEXT>When an event on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the interrupt vector at address $001. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PCIF</NAME>
<DESCRIPTION>Pin Change Interrupt Flag</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
</GIFR>
<PCMSK>
<NAME>PCMSK</NAME>
<DESCRIPTION>Pin Change Enable Mask</DESCRIPTION>
<TEXT/>
<IO_ADDR>$15</IO_ADDR>
<MEM_ADDR>$35</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT5>
<NAME>PCINT5</NAME>
<DESCRIPTION>Pin Change Enable Mask Bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PCINT4</NAME>
<DESCRIPTION>Pin Change Enable Mask Bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PCINT3</NAME>
<DESCRIPTION>Pin Change Enable Mask Bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PCINT2</NAME>
<DESCRIPTION>Pin Change Enable Mask Bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PCINT1</NAME>
<DESCRIPTION>Pin Change Enable Mask Bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PCINT0</NAME>
<DESCRIPTION>Pin Change Enable Mask Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PCMSK>
</EXTERNAL_INTERRUPT>
<EEPROM>
<LIST>[EEARL:EEARH:EEDR:EECR]</LIST>
<LINK/>
<ICON>io_cpu.bmp</ICON>
<ID/>
<TEXT>EEPROM Read/Write Access. The EEPROM access registers are accessible in the I/O space. The write access time for the EEPROM is given in Table 1. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V CC is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See “Preventing EEPROM Corruption” on page 19. for details on how to avoid problems in these situations.In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When theEEPROM is written, the CPU is halted for two clock cycles before the next instruction is execut</TEXT>
<EEARH>
<NAME>EEARH</NAME>
<DESCRIPTION>EEPROM Address Register High Byte</DESCRIPTION>
<TEXT/>
<IO_ADDR>$1F</IO_ADDR>
<MEM_ADDR>$3F</MEM_ADDR>
<ICON>io_cpu.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT0>
<NAME>EEAR8</NAME>
<DESCRIPTION>EEPROM Read/Write Access Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</EEARH>
<EEARL>
<NAME>EEARL</NAME>
<DESCRIPTION>EEPROM Address Register Low Byte</DESCRIPTION>
<TEXT/>
<IO_ADDR>$1E</IO_ADDR>
<MEM_ADDR>$3E</MEM_ADDR>
<ICON>io_cpu.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>EEAR7</NAME>
<DESCRIPTION>EEPROM Read/Write Access Bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>EEAR6</NAME>
<DESCRIPTION>EEPROM Read/Write Access Bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>EEAR5</NAME>
<DESCRIPTION>EEPROM Read/Write Access Bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>EEAR4</NAME>
<DESCRIPTION>EEPROM Read/Write Access Bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>EEAR3</NAME>
<DESCRIPTION>EEPROM Read/Write Access Bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>EEAR2</NAME>
<DESCRIPTION>EEPROM Read/Write Access Bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>EEAR1</NAME>
<DESCRIPTION>EEPROM Read/Write Access Bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>EEAR0</NAME>
<DESCRIPTION>EEPROM Read/Write Access Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</EEARL>
<EEDR>
<NAME>EEDR</NAME>
<DESCRIPTION>EEPROM Data Register</DESCRIPTION>
<TEXT>For the EEPROM write operation, the EEDR register contains the data to be written to the EEPROM in the address given by the EEAR register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR.</TEXT>
<IO_ADDR>$1D</IO_ADDR>
<MEM_ADDR>$3D</MEM_ADDR>
<ICON>io_cpu.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>EEDR7</NAME>
<DESCRIPTION>EEPROM Data Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>EEDR6</NAME>
<DESCRIPTION>EEPROM Data Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>EEDR5</NAME>
<DESCRIPTION>EEPROM Data Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>EEDR4</NAME>
<DESCRIPTION>EEPROM Data Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>EEDR3</NAME>
<DESCRIPTION>EEPROM Data Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>EEDR2</NAME>
<DESCRIPTION>EEPROM Data Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>EEDR1</NAME>
<DESCRIPTION>EEPROM Data Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>EEDR0</NAME>
<DESCRIPTION>EEPROM Data Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</EEDR>
<EECR>
<NAME>EECR</NAME>
<DESCRIPTION>EEPROM Control Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$1C</IO_ADDR>
<MEM_ADDR>$3C</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT5>
<NAME>EEPM1</NAME>
<DESCRIPTION>EEPROM Programming Mode Bit 1</DESCRIPTION>
<TEXT>The EEPROM Programming mode bit setting defines which programming action that will be triggered when writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the Erase and Write operations in two different operations. The Programming times for the different modes are shown in Table 2. While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>X</INIT_VAL>
</BIT5>
<BIT4>
<NAME>EEPM0</NAME>
<DESCRIPTION>EEPROM Programming Mode Bit 0</DESCRIPTION>
<TEXT>The EEPROM Programming mode bit setting defines which programming action that will be triggered when writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the Erase and Write operations in two different operations. The Programming times for the different modes are shown in Table 2. While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>X</INIT_VAL>
</BIT4>
<BIT3>
<NAME>EERIE</NAME>
<DESCRIPTION>EEPROM Ready Interrupt Enable</DESCRIPTION>
<TEXT>EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>EEMPE</NAME>
<DESCRIPTION>EEPROM Master Write Enable</DESCRIPTION>
<TEXT>The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is written to one, writing EEWE to one within 4 clock cycles will write data to the EEPROM at the selected address. If EEMWE is zero, writing EEWE to one will have no effect. When EEMWE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for an EEPROM write procedure.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>EEPE</NAME>
<DESCRIPTION>EEPROM Write Enable</DESCRIPTION>
<TEXT>The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential): 1. Wait until EEWE becomes zero. 2. Wait until SPMEN in SPMCR becomes zero. 3. Write new EEPROM address to EEAR (optional). 4. Write new EEPROM data to EEDR (optional). 5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR. 6. Within four clock cycles after setting EEMWE, write a logical one to EEWE. The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a boot loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See “Boot Loader Support - Read While Write self-programming” on page 228 for details about boot programming. Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR regis-ter will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during the 4 last steps to avoid these problems. When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruc-tion is executed</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>X</INIT_VAL>
</BIT1>
<BIT0>
<NAME>EERE</NAME>
<DESCRIPTION>EEPROM Read Enable</DESCRIPTION>
<TEXT>The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR register. The calibrated oscillator is used to time the EEPROM accesses. Table 1 lists the typical programming time for EEPROM access from the CPU</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</EECR>
</EEPROM>
<WATCHDOG>
<LIST>[WDTCR]</LIST>
<LINK/>
<ICON>io_watch.bmp</ICON>
<ID/>
<TEXT/>
<WDTCR>
<NAME>WDTCR</NAME>
<ALIAS>WDTCSR</ALIAS>
<DESCRIPTION>Watchdog Timer Control Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$21</IO_ADDR>
<MEM_ADDR>$41</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>WDIF</NAME>
<DESCRIPTION>Watchdog Timeout Interrupt Flag</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>WDIE</NAME>
<DESCRIPTION>Watchdog Timeout Interrupt Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>WDP3</NAME>
<DESCRIPTION>Watchdog Timer Prescaler Bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>WDCE</NAME>
<ALIAS>WDTOE</ALIAS>
<DESCRIPTION>Watchdog Change Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>WDE</NAME>
<DESCRIPTION>Watch Dog Enable</DESCRIPTION>
<TEXT>When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>WDP2</NAME>
<DESCRIPTION>Watch Dog Timer Prescaler bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>WDP1</NAME>
<DESCRIPTION>Watch Dog Timer Prescaler bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>WDP0</NAME>
<DESCRIPTION>Watch Dog Timer Prescaler bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</WDTCR>
</WATCHDOG>
<TIMER_COUNTER_0>
<LIST>[TIMSK:TIFR:TCCR0A:TCCR0B:TCNT0:OCR0A:OCR0B:GTCCR]</LIST>
<LINK/>
<ICON>io_timer.bmp</ICON>
<ID/>
<TEXT/>
<TIMSK>
<NAME>TIMSK</NAME>
<DESCRIPTION>Timer/Counter Interrupt Mask Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$39</IO_ADDR>
<MEM_ADDR>$59</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT4>
<NAME>OCIE0A</NAME>
<DESCRIPTION>Timer/Counter0 Output Compare Match A Interrupt Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCIE0B</NAME>
<DESCRIPTION>Timer/Counter0 Output Compare Match B Interrupt Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT1>
<NAME>TOIE0</NAME>
<DESCRIPTION>Timer/Counter0 Overflow Interrupt Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
</TIMSK>
<TIFR>
<NAME>TIFR</NAME>
<DESCRIPTION>Timer/Counter0 Interrupt Flag register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$38</IO_ADDR>
<MEM_ADDR>$58</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT4>
<NAME>OCF0A</NAME>
<DESCRIPTION>Timer/Counter0 Output Compare Flag 0A</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCF0B</NAME>
<DESCRIPTION>Timer/Counter0 Output Compare Flag 0B</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT1>
<NAME>TOV0</NAME>
<DESCRIPTION>Timer/Counter0 Overflow Flag</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
</TIFR>
<TCCR0A>
<NAME>TCCR0A</NAME>
<DESCRIPTION>Timer/Counter Control Register A</DESCRIPTION>
<TEXT/>
<IO_ADDR>$2A</IO_ADDR>
<MEM_ADDR>$4A</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>COM0A1</NAME>
<DESCRIPTION>Compare Output Mode, Phase Correct PWM Mode</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>COM0A0</NAME>
<DESCRIPTION>Compare Output Mode, Phase Correct PWM Mode</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>COM0B1</NAME>
<DESCRIPTION>Compare Output Mode, Fast PWm</DESCRIPTION>
<TEXT/>
<ACCESS>W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>COM0B0</NAME>
<DESCRIPTION>Compare Output Mode, Fast PWm</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT1>
<NAME>WGM01</NAME>
<DESCRIPTION>Waveform Generation Mode</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>WGM00</NAME>
<DESCRIPTION>Waveform Generation Mode</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCCR0A>
<TCCR0B>
<NAME>TCCR0B</NAME>
<DESCRIPTION>Timer/Counter Control Register B</DESCRIPTION>
<TEXT/>
<IO_ADDR>$33</IO_ADDR>
<MEM_ADDR>$53</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>FOC0A</NAME>
<DESCRIPTION>Force Output Compare A</DESCRIPTION>
<TEXT/>
<ACCESS>W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>FOC0B</NAME>
<DESCRIPTION>Force Output Compare B</DESCRIPTION>
<TEXT/>
<ACCESS>W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT3>
<NAME>WGM02</NAME>
<DESCRIPTION/>
<TEXT/>
<ACESS>RW</ACESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>CS02</NAME>
<DESCRIPTION>Clock Select</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>CS01</NAME>
<DESCRIPTION>Clock Select</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>CS00</NAME>
<DESCRIPTION>Clock Select</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCCR0B>
<TCNT0>
<NAME>TCNT0</NAME>
<DESCRIPTION>Timer/Counter0</DESCRIPTION>
<TEXT>The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT0 register blocks (removes) the compare match on the following timer clock. Modifying the counter (TCNT0) while the counter is running, introduces a risk of missing a compare match between TCNT0 the OCR0 register.</TEXT>
<IO_ADDR>$32</IO_ADDR>
<MEM_ADDR>$52</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>TCNT0_7</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TCNT0_6</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>TCNT0_5</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>TCNT0_4</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>TCNT0_3</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>TCNT0_2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>TCNT0_1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TCNT0_0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCNT0>
<OCR0A>
<NAME>OCR0A</NAME>
<DESCRIPTION>Timer/Counter0 Output Compare Register</DESCRIPTION>
<TEXT>The Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC0 pin.</TEXT>
<IO_ADDR>$29</IO_ADDR>
<MEM_ADDR>$49</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR0_7</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR0_6</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR0_5</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR0_4</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR0_3</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR0_2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR0_1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR0_0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR0A>
<OCR0B>
<NAME>OCR0B</NAME>
<DESCRIPTION>Timer/Counter0 Output Compare Register</DESCRIPTION>
<TEXT>The Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC0 pin.</TEXT>
<IO_ADDR>$28</IO_ADDR>
<MEM_ADDR>$48</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR0_7</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR0_6</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR0_5</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR0_4</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR0_3</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR0_2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR0_1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR0_0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR0B>
<GTCCR>
<NAME>GTCCR</NAME>
<DESCRIPTION>General Timer/Counter Control Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$2C</IO_ADDR>
<MEM_ADDR>$4C</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>TSM</NAME>
<DESCRIPTION>Timer/Counter Synchronization Mode</DESCRIPTION>
<TEXT>Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSR2 and PSR10 bits is kept, hence keeping the corresponding prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can be configured to the same value without the risk of one of them advancing during configuration. When the TSM bit is written to zero, the PSR2 and PSR10 bits are cleared by hardware, and the Timer/Counters start counting simultaneousl</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT0>
<NAME>PSR0</NAME>
<DESCRIPTION>Prescaler Reset Timer/Counter1 and Timer/Counter0</DESCRIPTION>
<TEXT>When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</GTCCR>
</TIMER_COUNTER_0>
<TIMER_COUNTER_1>
<LIST>[TCCR1:TCNT1:OCR1A:OCR1B:OCR1C:TIMSK:TIFR:GTCCR:DTPS:DTVALA:DTVALB]</LIST>
<LINK/>
<ICON>io_timer.bmp</ICON>
<ID>t8pwm1_02</ID>
<TEXT/>
<TCCR1>
<NAME>TCCR1</NAME>
<DESCRIPTION>Timer/Counter Control Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$30</IO_ADDR>
<MEM_ADDR>$50</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>CTC1</NAME>
<DESCRIPTION>Clear Timer/Counter on Compare Match</DESCRIPTION>
<TEXT>When the CTC1 control bit is set (one), Timer/Counter1 is reset to $00 in the CPU clock cycle after a compare match with OCR1A register value. If the control bit is cleared, Timer/Counter1 continues counting and is unaffected by a compare match.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PWM1A</NAME>
<DESCRIPTION>Pulse Width Modulator Enable</DESCRIPTION>
<TEXT>When set (one), this bit enables PWM mode for Timer/Counter1.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>COM1A1</NAME>
<DESCRIPTION>Compare Output Mode, Bit 0</DESCRIPTION>
<TEXT>The COM1A1 and COM1A0 control bits determine any output pin action following a compare match A in Timer/Counter1. Output pin actions affect pin PB1(OC1A). Since this is an alternative function to an I/O port, the corresponding direction control bit must be set (one) to control an output pin.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>COM1A0</NAME>
<DESCRIPTION>Compare Output Mode, Bit 1</DESCRIPTION>
<TEXT>The COM1A1 and COM1A0 control bits determine any output pin action following a compare match A in Timer/Counter1. Output pin actions affect pin PB1(OC1A). Since this is an alternative function to an I/O port, the corresponding direction control bit must be set (one) to control an output pin.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>CS13</NAME>
<DESCRIPTION>Clock Select Bits</DESCRIPTION>
<TEXT>The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>CS12</NAME>
<DESCRIPTION>Clock Select Bits</DESCRIPTION>
<TEXT>The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>CS11</NAME>
<DESCRIPTION>Clock Select Bits</DESCRIPTION>
<TEXT>The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>CS10</NAME>
<DESCRIPTION>Clock Select Bits</DESCRIPTION>
<TEXT>The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCCR1>
<TCNT1>
<NAME>TCNT1</NAME>
<DESCRIPTION>Timer/Counter Register</DESCRIPTION>
<TEXT>The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT1 register blocks (removes) the compare match on the following timer clock. Modifying the counter (TCNT1) while the counter is running, introduces a risk of missing a compare match between TCNT1 the OCR2 register. </TEXT>
<IO_ADDR>$2F</IO_ADDR>
<MEM_ADDR>$4F</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>TCNT1_7</NAME>
<DESCRIPTION>Timer/Counter Register Bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TCNT1_6</NAME>
<DESCRIPTION>Timer/Counter Register Bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>TCNT1_5</NAME>
<DESCRIPTION>Timer/Counter Register Bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>TCNT1_4</NAME>
<DESCRIPTION>Timer/Counter Register Bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>TCNT1_3</NAME>
<DESCRIPTION>Timer/Counter Register Bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>TCNT1_2</NAME>
<DESCRIPTION>Timer/Counter Register Bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>TCNT1_1</NAME>
<DESCRIPTION>Timer/Counter Register Bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TCNT1_0</NAME>
<DESCRIPTION>Timer/Counter Register Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCNT1>
<OCR1A>
<NAME>OCR1A</NAME>
<DESCRIPTION>Output Compare Register</DESCRIPTION>
<TEXT>The Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT1). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC2 pin.</TEXT>
<IO_ADDR>$2E</IO_ADDR>
<MEM_ADDR>$4E</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR1A7</NAME>
<DESCRIPTION>Output Compare Register A Bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR1A6</NAME>
<DESCRIPTION>Output Compare Register A Bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR1A5</NAME>
<DESCRIPTION>Output Compare Register A Bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR1A4</NAME>
<DESCRIPTION>Output Compare Register A Bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR1A3</NAME>
<DESCRIPTION>Output Compare Register A Bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR1A2</NAME>
<DESCRIPTION>Output Compare Register A Bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR1A1</NAME>
<DESCRIPTION>Output Compare Register A Bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR1A0</NAME>
<DESCRIPTION>Output Compare Register A Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR1A>
<OCR1B>
<NAME>OCR1B</NAME>
<DESCRIPTION>Output Compare Register</DESCRIPTION>
<TEXT>The Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT1). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC2 pin.</TEXT>
<IO_ADDR>$2B</IO_ADDR>
<MEM_ADDR>$4B</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR1B7</NAME>
<DESCRIPTION>Output Compare Register B Bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR1B6</NAME>
<DESCRIPTION>Output Compare Register B Bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR1B5</NAME>
<DESCRIPTION>Output Compare Register B Bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR1B4</NAME>
<DESCRIPTION>Output Compare Register B Bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR1B3</NAME>
<DESCRIPTION>Output Compare Register B Bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR1B2</NAME>
<DESCRIPTION>Output Compare Register B Bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR1B1</NAME>
<DESCRIPTION>Output Compare Register B Bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR1B0</NAME>
<DESCRIPTION>Output Compare Register B Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR1B>
<OCR1C>
<NAME>OCR1C</NAME>
<DESCRIPTION>Output compare register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$2D</IO_ADDR>
<MEM_ADDR>$4D</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR1C7</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS/>
<INIT_VAL/>
</BIT7>
<BIT6>
<NAME>OCR1C6</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS/>
<INIT_VAL/>
</BIT6>
<BIT5>
<NAME>OCR1C5</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS/>
<INIT_VAL/>
</BIT5>
<BIT4>
<NAME>OCR1C4</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS/>
<INIT_VAL/>
</BIT4>
<BIT3>
<NAME>OCR1C3</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS/>
<INIT_VAL/>
</BIT3>
<BIT2>
<NAME>OCR1C2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS/>
<INIT_VAL/>
</BIT2>
<BIT1>
<NAME>OCR1C1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS/>
<INIT_VAL/>
</BIT1>
<BIT0>
<NAME>OCR1C0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS/>
<INIT_VAL/>
</BIT0>
</OCR1C>
<TIMSK>
<NAME>TIMSK</NAME>
<DESCRIPTION>Timer/Counter Interrupt Mask Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$39</IO_ADDR>
<MEM_ADDR>$59</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT6>
<NAME>OCIE1A</NAME>
<DESCRIPTION>OCIE1A: Timer/Counter1 Output Compare Interrupt Enable</DESCRIPTION>
<TEXT>When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Compare Match, interrupt is enabled. The corresponding interrupt (at vector $003) is executed if a compare match A in Timer/Counter1 occurs, i.e., when the OCF1A bit is set (one) in the Timer/Counter Interrupt Flag Register (TIFR).</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCIE1B</NAME>
<DESCRIPTION>OCIE1A: Timer/Counter1 Output Compare B Interrupt Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT2>
<NAME>TOIE1</NAME>
<DESCRIPTION>Timer/Counter1 Overflow Interrupt Enable</DESCRIPTION>
<TEXT>When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $004) is executed if an overflow in Timer/Counter1 occurs (i.e., when the TOV1 bit is set in the Timer/Counter Interrupt Flag Register [TIFR]).</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
</TIMSK>
<TIFR>
<NAME>TIFR</NAME>
<DESCRIPTION>Timer/Counter Interrupt Flag Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$38</IO_ADDR>
<MEM_ADDR>$58</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT6>
<NAME>OCF1A</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Flag 1A</DESCRIPTION>
<TEXT>The OCF1A bit is set (one) when compare match occurs between Timer/Counter1 and the data value in OCR1A (Output Compare Register 1A). OCF1A is cleared by hard-ware when executing the corresponding interrupt handling vector. Alternatively, OCF1A is cleared by writing a logical “1” to the flag. When the I-bit in SREG, OCIE1A, and OCF1A are set (one), the Timer/Counter1 compare match A interrupt is executed.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCF1B</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Flag 1B</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT2>
<NAME>TOV1</NAME>
<DESCRIPTION>Timer/Counter1 Overflow Flag</DESCRIPTION>
<TEXT>The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logical “1” to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overf low Interrupt Enable) and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
</TIFR>
<GTCCR>
<NAME>GTCCR</NAME>
<DESCRIPTION>Timer counter control register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$2C</IO_ADDR>
<MEM_ADDR>$4C</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<BIT6>
<NAME>PWM1B</NAME>
<DESCRIPTION>Pulse Width Modulator B Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>COM1B1</NAME>
<DESCRIPTION>Comparator B Output Mode</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>COM1B0</NAME>
<DESCRIPTION>Comparator B Output Mode</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>FOC1B</NAME>
<DESCRIPTION>Force Output Compare Match 1B</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>FOC1A</NAME>
<DESCRIPTION>Force Output Compare 1A</DESCRIPTION>
<TEXT>Writing a logical “1” to this bit forces a change in the compare match output pin PB1 (OC1A) according to the values already set in COM1A1 and COM1A0. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in timer. The automatic action programmed in COM1A1 and COM1A0 happens as if a Compare Match had occurred, but no interrupt is generated and the Timer/Counter1 will not be cleared even if CTC1 is set. The FOC1A bit will always be read as zero. The setting of the FOC1A bit has no effect i</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PSR1</NAME>
<DESCRIPTION>Prescaler Reset Timer/Counter1</DESCRIPTION>
<TEXT>When this bit is set (one) the Timer/Counter1 prescaler will be reset. The bit will be cleared by hardware after the operation is performed. Writing a “0” to this bit will have no effect. This bit will always be read as zero.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
</GTCCR>
<DTPS>
<NAME>DTPS</NAME>
<DESCRIPTION>Dead time prescaler register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$23</IO_ADDR>
<MEM_ADDR>$43</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<BIT1>
<NAME>DTPS1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>DTPS0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</DTPS>
<DTVALA>
<NAME>DTVALA</NAME>
<DESCRIPTION>Dead time value register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$25</IO_ADDR>
<MEM_ADDR>$45</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<BIT7>
<NAME>DTVH3</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>DTVH2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>DTVH1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>DTVH0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>DTVL3</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>DTVL2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>DTVL1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>DTVL0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</DTVALA>
<DTVALB>
<NAME>DTVALB</NAME>
<DESCRIPTION>Dead time value B</DESCRIPTION>
<TEXT/>
<IO_ADDR>$24</IO_ADDR>
<MEM_ADDR>$44</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<BIT7>
<NAME>DTVH3</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>DTVH2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>DTVH1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>DTVH0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>DTVL3</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>DTVL2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>DTVL1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>DTVL0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</DTVALB>
</TIMER_COUNTER_1>
<CPU>
<LIST>[SREG:SPH:SPL:MCUCR:MCUSR:PRR:OSCCAL:PLLCSR:CLKPR:DWDR:GPIOR2:GPIOR1:GPIOR0]</LIST>
<LINK>[SPH:SPL]</LINK>
<ICON>io_cpu.bmp</ICON>
<ID/>
<TEXT/>
<SREG>
<NAME>SREG</NAME>
<DESCRIPTION>Status Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$3F</IO_ADDR>
<MEM_ADDR>$5F</MEM_ADDR>
<ICON>io_sreg.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>I</NAME>
<DESCRIPTION>Global Interrupt Enable</DESCRIPTION>
<TEXT>The global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the global interrupt enable bit is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>T</NAME>
<DESCRIPTION>Bit Copy Storage</DESCRIPTION>
<TEXT>The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source and destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>H</NAME>
<DESCRIPTION>Half Carry Flag</DESCRIPTION>
<TEXT>The half carry flag H indicates a half carry in some arithmetic operations. See the Instruction Set Description for detailed information.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>S</NAME>
<DESCRIPTION>Sign Bit</DESCRIPTION>
<TEXT>The S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the Instruc-tion Set Description for detailed information.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>V</NAME>
<DESCRIPTION>Two's Complement Overflow Flag</DESCRIPTION>
<TEXT>The two’s complement overflow flag V supports two’s complement arithmetics. See the Instruction Set Description for detailed information.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>N</NAME>
<DESCRIPTION>Negative Flag</DESCRIPTION>
<TEXT>The negative flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>Z</NAME>
<DESCRIPTION>Zero Flag</DESCRIPTION>
<TEXT>The zero flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>C</NAME>
<DESCRIPTION>Carry Flag</DESCRIPTION>
<TEXT>The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</SREG>
<PRR>
<NAME>PRR</NAME>
<DESCRIPTION>Power Reduction Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$20</IO_ADDR>
<MEM_ADDR>$40</MEM_ADDR>
<ICON>io_sreg.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT3>
<NAME>PRTIM1</NAME>
<DESCRIPTION>Power Reduction Timer/Counter1</DESCRIPTION>
<TEXT>Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1 is enabled, operation will continue like before the shutdown.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PRTIM0</NAME>
<DESCRIPTION>Power Reduction Timer/Counter0</DESCRIPTION>
<TEXT>Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0 is enabled, operation will continue like before the shutdown.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PRUSI</NAME>
<DESCRIPTION>Power Reduction USI</DESCRIPTION>
<TEXT>Writing a logic one to this bit shuts down the USI by stopping the clock to the module. When waking up the USI again, the USI should be re initialized to ensure proper operation.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PRADC</NAME>
<DESCRIPTION>Power Reduction ADC</DESCRIPTION>
<TEXT>Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down. The analog comparator cannot use the ADC input MUX when the ADC is shut down.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PRR>
<SPH>
<NAME>SPH</NAME>
<DESCRIPTION>Stack Pointer High Byte</DESCRIPTION>
<TEXT/>
<IO_ADDR>$3E</IO_ADDR>
<MEM_ADDR>$5E</MEM_ADDR>
<ICON>io_sreg.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT0>
<NAME>SP8</NAME>
<DESCRIPTION>Stack Pointer Bit 8</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</SPH>
<SPL>
<NAME>SPL</NAME>
<DESCRIPTION>Stack Pointer Low Byte</DESCRIPTION>
<TEXT/>
<IO_ADDR>$3D</IO_ADDR>
<MEM_ADDR>$5D</MEM_ADDR>
<ICON>io_sreg.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>SP7</NAME>
<DESCRIPTION>Stack Pointer Bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>SP6</NAME>
<DESCRIPTION>Stack Pointer Bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>SP5</NAME>
<DESCRIPTION>Stack Pointer Bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>SP4</NAME>
<DECRIPTION>Stack Pointer Bit 4</DECRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>SP3</NAME>
<DESCRIPTION>Stack Pointer Bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>SP2</NAME>
<DESCRIPTION>Stack Pointer Bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>SP1</NAME>
<DESCRIPTION>Stack Pointer Bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>SP0</NAME>
<DESCRIPTION>Stack Pointer Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</SPL>
<MCUCR>
<NAME>MCUCR</NAME>
<DESCRIPTION>MCU Control Register</DESCRIPTION>
<TEXT>The MCU Control Register contains control bits for general MCU functions.</TEXT>
<IO_ADDR>$35</IO_ADDR>
<MEM_ADDR>$55</MEM_ADDR>
<ICON>io_cpu.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT6>
<NAME>PUD</NAME>
<DESCRIPTION>Pull-up Disable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>SE</NAME>
<DESCRIPTION>Sleep Enable</DESCRIPTION>
<TEXT>The SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmers purpose, it is recommended to set the Sleep Enable SE bit just before the execution of the SLEEP instruction.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>SM1</NAME>
<DESCRIPTION>Sleep Mode Select Bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>SM0</NAME>
<DESCRIPTION>Sleep Mode Select Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT1>
<NAME>ISC01</NAME>
<DESCRIPTION>Interrupt Sense Control 0 bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>ISC00</NAME>
<DESCRIPTION>Interrupt Sense Control 0 bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</MCUCR>
<MCUSR>
<NAME>MCUSR</NAME>
<DESCRIPTION>MCU Status register</DESCRIPTION>
<TEXT>The MCU Status Registerprovides information on which reset source caused a MCU reset.</TEXT>
<IO_ADDR>$34</IO_ADDR>
<MEM_ADDR>$54</MEM_ADDR>
<ICON>io_cpu.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT3>
<NAME>WDRF</NAME>
<DESCRIPTION>Watchdog Reset Flag</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>BORF</NAME>
<DESCRIPTION>Brown-out Reset Flag</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>EXTRF</NAME>
<DESCRIPTION>External Reset Flag</DESCRIPTION>
<TEXT>After a power-on reset, this bit is undefined (X). It will be set by an external reset. A watchdog reset will leave this bit unchanged.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PORF</NAME>
<DESCRIPTION>Power-On Reset Flag</DESCRIPTION>
<TEXT>This bit is set by a power-on reset. A watchdog reset or an external reset will leave this bit unchanged</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</MCUSR>
<OSCCAL>
<NAME>OSCCAL</NAME>
<DESCRIPTION>Oscillator Calibration Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$31</IO_ADDR>
<MEM_ADDR>$51</MEM_ADDR>
<ICON>io_sreg.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>CAL7</NAME>
<DESCRIPTION>Oscillatro Calibration Value Bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>CAL6</NAME>
<DESCRIPTION>Oscillatro Calibration Value Bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>CAL5</NAME>
<DESCRIPTION>Oscillatro Calibration Value Bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>CAL4</NAME>
<DESCRIPTION>Oscillatro Calibration Value Bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>CAL3</NAME>
<DESCRIPTION>Oscillatro Calibration Value Bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>CAL2</NAME>
<DESCRIPTION>Oscillatro Calibration Value Bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>CAL1</NAME>
<DESCRIPTION>Oscillatro Calibration Value Bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>CAL0</NAME>
<DESCRIPTION>Oscillatro Calibration Value Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OSCCAL>
<CLKPR>
<NAME>CLKPR</NAME>
<DESCRIPTION>Clock Prescale Register</DESCRIPTION>
<TEXT>The system clock can be divided by setting the Clock Prescale Register – CLKPR. This feature can be used to decrease power consumption when the requirement for processing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals.</TEXT>
<IO_ADDR>$26</IO_ADDR>
<MEM_ADDR>$46</MEM_ADDR>
<ICON>io_sreg.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>CLKPCE</NAME>
<DESCRIPTION>Clock Prescaler Change Enable</DESCRIPTION>
<TEXT>The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only update when the other bits in CLKPR are simultaniosly written to zero. CLKPCE is cleared by hardware four cycles after it is written or when CLKPS is written. Rewriting the CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the CLKPCE bit.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT3>
<NAME>CLKPS3</NAME>
<DESCRIPTION>Clock Prescaler Select Bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>CLKPS2</NAME>
<DESCRIPTION>Clock Prescaler Select Bit 2</DESCRIPTION>
<TEXT>These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used. The division factors are given a table in the device user guide.. To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the CLKPS bits: 1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero. 2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE. Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>CLKPS1</NAME>
<DESCRIPTION>Clock Prescaler Select Bit 1</DESCRIPTION>
<TEXT>These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used. The division factors are given a table in the device user guide.. To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the CLKPS bits: 1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero. 2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE. Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>CLKPS0</NAME>
<DESCRIPTION>Clock Prescaler Select Bit 0</DESCRIPTION>
<TEXT>These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used. The division factors are given a table in the device user guide.. To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the CLKPS bits: 1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero. 2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE. Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</CLKPR>
<PLLCSR>
<NAME>PLLCSR</NAME>
<DESCRIPTION>PLL Control and status register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$27</IO_ADDR>
<MEM_ADDR>$47</MEM_ADDR>
<ICON>io_sreg.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>LSM</NAME>
<DESCRIPTION>Low speed mode</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT2>
<NAME>PCKE</NAME>
<DESCRIPTION>PCK Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PLLE</NAME>
<DESCRIPTION>PLL Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PLOCK</NAME>
<DESCRIPTION>PLL Lock detector</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PLLCSR>
<DWDR>
<NAME>DWDR</NAME>
<DESCRIPTION>debugWire data register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$22</IO_ADDR>
<MEM_ADDR>$42</MEM_ADDR>
<ICON>io_cpu.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>DWDR7</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>DWDR6</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>DWDR5</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>DWDR4</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>DWDR3</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>DWDR2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>DWDR1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>DWDR0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</DWDR>
<GPIOR2>
<NAME>GPIOR2</NAME>
<DESCRIPTION>General Purpose IO register 2</DESCRIPTION>
<TEXT/>
<IO_ADDR>$13</IO_ADDR>
<MEM_ADDR>$33</MEM_ADDR>
<ICON>io_sreg.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>GPIOR27</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>GPIOR26</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>GPIOR25</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>GPIOR24</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>GPIOR23</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>GPIOR22</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>GPIOR21</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>GPIOR20</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>GPIOR27</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</GPIOR2>
<GPIOR1>
<NAME>GPIOR1</NAME>
<DESCRIPTION>General Purpose register 1</DESCRIPTION>
<TEXT/>
<IO_ADDR>$12</IO_ADDR>
<MEM_ADDR>$32</MEM_ADDR>
<ICON>io_sreg.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>GPIOR17</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>GPIOR16</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>GPIOR15</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>GPIOR14</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>GPIOR13</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>GPIOR12</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>GPIOR11</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>GPIOR10</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</GPIOR1>
<GPIOR0>
<NAME>GPIOR0</NAME>
<DESCRIPTION>General purpose register 0</DESCRIPTION>
<TEXT/>
<IO_ADDR>$11</IO_ADDR>
<MEM_ADDR>$31</MEM_ADDR>
<ICON>io_sreg.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>GPIOR07</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>GPIOR06</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>GPIOR05</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>GPIOR04</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>9</INIT_VAL>
</BIT4>
<BIT3>
<NAME>GPIOR03</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>GPIOR02</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>GPIOR01</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>GPIOR00</NAME>
<DESCRIPTION/>
<TEXT>RW</TEXT>
<ACCESS>0</ACCESS>
<INIT_VAL/>
</BIT0>
</GPIOR0>
</CPU>
<BOOT_LOAD>
<LIST>[SPMCSR]</LIST>
<LINK/>
<RULES/>
<ICON>io_cpu.bmp</ICON>
<ID/>
<TEXT>The Boot Loader Support provides a real Read While Write self-programming mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates controlled by the MCU using a Flash-resident Boot Loader program. The Boot Loader program can use any available data interface and associated proto-col to read code and write (program) that code into the Flash memory, or read the code from the program memory. The program code within the Boot Loader section has the capability to write into the entire Flash, including the Boot Loader Memory. The Boot Loader can thus even modify itself, and it can also erase itself from the code if the feature is not needed anymore. The size of the Boot Loader Memory is configurable with fuses and the Boot Loader has two separate sets of Boot Lock Bits which can be set independently. This gives the user a unique flexibility to select different levels of protection. Boot Loader Features: Read While Write self-programming. Flexibl Boot Memory size. High security (separate Boot Lock bits for a flexible protection). Separate fuse to select reset vector Optimized page (1) size. Code efficient algorithm Efficient read-modify-write suppo</TEXT>
<SPMCSR>
<NAME>SPMCSR</NAME>
<DESCRIPTION>Store Program Memory Control Register</DESCRIPTION>
<TEXT>The Store Program Memory Control Register contains the control bits needed to control the Boot Loader operations.</TEXT>
<IO_ADDR>$37</IO_ADDR>
<MEM_ADDR>$57</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT4>
<NAME>CTPB</NAME>
<DESCRIPTION>Clear temporary page buffer</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>RFLB</NAME>
<DESCRIPTION>Read fuse and lock bits</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PGWRT</NAME>
<DESCRIPTION>Page Write</DESCRIPTION>
<TEXT>If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a page write, or if no SPM instruction is exe-cuted within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PGERS</NAME>
<DESCRIPTION>Page Erase</DESCRIPTION>
<TEXT>If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page erase. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a page erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>SPMEN</NAME>
<DESCRIPTION>Store Program Memory Enable</DESCRIPTION>
<TEXT>This bit enables the SPM instruction for the next four clock cycles. If written to one together with either RWWSRE, BLB-SET, PGWRT or PGERS, the following SPM instruction will have a special meaning, see description above. If only SPMEN is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z pointer. The LSB of the Z pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction, or if no SPM instruction is executed within four clock cycles. During page erase and page write, the SPMEN bit remain high until the operation is completed. Writing any other combination than “10001”, "01001", "00101", "00011" or "00001" in the lower five bits will have no eff</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</SPMCSR>
</BOOT_LOAD>
</IO_MODULE><ICE_SETTINGS><MODULE_LIST>[SIMULATOR:JTAGICEmkII:STK500:STK500_2:ICE50:AVRISPmkII:AVRDragon]</MODULE_LIST><SIMULATOR>
<CoreID>AVRSimCoreV2.SimCoreV2</CoreID>
<MemoryID>AVRSimMemory8bit.SimMemory8bit</MemoryID>
<InterruptID>AVRSimInterrupt.SimInterrupt</InterruptID>
<EEINTERRUPT>0x06</EEINTERRUPT>
<EEAR_EXTRA_BIT>0</EEAR_EXTRA_BIT>
<NmbIOModules>6</NmbIOModules>
<PORTB>
<ID>AVRSimIOPort.SimIOPort</ID>
<TOGGLE_PIN>Y</TOGGLE_PIN>
</PORTB>
<EXTINT0>
<ID>AVRSimIOExtInterrupt.SimIOExtInterrupt</ID>
<IntVector>0x01</IntVector>
<EnableIOAdr>0x3b</EnableIOAdr>
<EnableMask>0x40</EnableMask>
<FlagIOAdr>0x3a</FlagIOAdr>
<FlagMask>0x40</FlagMask>
<ExtPinIOAdr>0x16</ExtPinIOAdr>
<ExtPinMask>0x04</ExtPinMask>
<SenseIOAdr>0x35</SenseIOAdr>
<SenseMask>0x03</SenseMask>
</EXTINT0>
<PININT0>
<ID>AVRSimIOPinChangeInterrupt.SimIOPinChangeInterrupt</ID>
<IntVector>0x02</IntVector>
<EnableIOAdr>0x3B</EnableIOAdr>
<EnableMask>0x20</EnableMask>
<FlagIOAdr>0x3A</FlagIOAdr>
<FlagMask>0x20</FlagMask>
<PCMaskIOAdr>0x15</PCMaskIOAdr>
<ExtPinIOAdr>0x16</ExtPinIOAdr>
<ExtPinMask>0x3F</ExtPinMask>
</PININT0>
<ANALOGCOMPARATOR>
<ID>AVRSimAC.SimIOAC</ID>
<IntVector>0x07</IntVector>
</ANALOGCOMPARATOR>
<ADC>
<ID>AVRSimADC.SimADC</ID>
<IntVector>0x08</IntVector>
</ADC>
<TIMER0>
<ID>AvrSimIOTim8pwmsync2.tim8pwmsync2</ID>
<OvfVector>0x05</OvfVector>
<CompAVector>0x0a</CompAVector>
<CompBVector>0x0b</CompBVector>
<OCnAport>PORTB</OCnAport>
<OCnAbit>0</OCnAbit>
<OCnBport>PORTB</OCnBport>
<OCnBbit>1</OCnBbit>
<TxPort>PINB</TxPort>
<TxBit>2</TxBit>
</TIMER0>
<!-- <TIMER1>
<ID>AVRSimIOTimer8pll_OCABC.SimIOTimer8pll_OCABC</ID>
<CompAVector>0x03</CompAVector>
<CompBVector>0x09</CompBVector>
<OvfVector>0x04</OvfVector>
<OutputAdr>0x16</OutputAdr>
<DirectionAdr>0x17</DirectionAdr>
<OutputAMask>0x02</OutputAMask>
<OutputBMask>0x10</OutputBMask>
<OutputAMaskNeg>0x01</OutputAMaskNeg>
<OutputBMaskNeg>0x08</OutputBMaskNeg>
</TIMER1>
-->
</SIMULATOR>
<JTAGICEmkII>
<ID>0x9206</ID>
<Interface>DebugWire</Interface>
<!--Bit 0 in byte 0 is I/O location, bit 7 in byte 7 is I/O location 63-->
<ucRead>0xF8,0xE1,0xFF,0xF1,0xFB,0xFF,0xBF,0xEF</ucRead>
<ucWrite>0xC8,0xE1,0xFF,0x71,0xBB,0x7F,0xAD,0xEB</ucWrite>
<ucReadShadow>0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00</ucReadShadow>
<ucWriteShadow>0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00</ucWriteShadow>
<!--Bit 0 in byte 0 is extended I/O location, bit 7 in byte 7 is I/O location 63-->
<ucExtRead>0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00</ucExtRead>
<ucExtWrite>0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00</ucExtWrite>
<ucExtReadShadow>0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00</ucExtReadShadow>
<ucExtWriteShadow>0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00</ucExtWriteShadow>
<!--Register locations etc.-->
<ucIDRAddress>0x00</ucIDRAddress>
<ucSPMCAddress>0X00</ucSPMCAddress>
<ucRAMPZAddress>0X00</ucRAMPZAddress>
<ulFlashPageSize>64</ulFlashPageSize>
<ulEepromPageSize>4</ulEepromPageSize>
<ulBootAddress>0x0000</ulBootAddress>
<BootAddress11>0x0000</BootAddress11>
<BootAddress10>0x0000</BootAddress10>
<BootAddress01>0x0000</BootAddress01>
<BootAddress00>0x0000</BootAddress00>
<ucUpperExtIOLoc>0x00</ucUpperExtIOLoc>
<ulFlashSize>0x1000</ulFlashSize>
<ulRegStart>0x0000,32</ulRegStart>
<ulIoStart>0x0020,64</ulIoStart>
<!--Other stuff-->
<DWENmaskExt>0x00</DWENmaskExt>
<DWENmaskHigh>0x40</DWENmaskHigh>
<DWENmaskLow>0x00</DWENmaskLow>
<SPIENmaskExt>0x00</SPIENmaskExt>
<SPIENmaskHigh>0x20</SPIENmaskHigh>
<SPIENmaskLow>0x00</SPIENmaskLow>
<ucEepromInst>0xBB, 0xFF, 0xBB, 0xEE, 0xBB, 0xCC, 0xB2, 0x0D, 0xBC, 0x02, 0xB4, 0x02, 0xBA, 0x0D, 0xBB, 0xBC, 0x99, 0xE1, 0xBB, 0xAC</ucEepromInst>
<ucFlashInst>0xB4, 0x02, 0x12</ucFlashInst>
<ucSPHaddr>0x3e</ucSPHaddr>
<ucSPLaddr>0x3d</ucSPLaddr>
<DWdatareg>0x22</DWdatareg>
<DWbasePC>0x00</DWbasePC>
<Osccalshared>0x00</Osccalshared>
<ucAllowFullPageBitstream>0x00</ucAllowFullPageBitstream>
<uiStartSmallestBootLoaderSection>0x00</uiStartSmallestBootLoaderSection>
<ucUseJTAGID>0x00</ucUseJTAGID>
<EECRAddress>0x1c</EECRAddress>
</JTAGICEmkII>
<STK500>
<DeviceId>0x14</DeviceId>
<SelfTimed>1</SelfTimed>
<FullParallel>0</FullParallel>
<Polled>1</Polled>
<FPoll>0xFF</FPoll>
<EPol1>0xFF</EPol1>
<EPol2>0xFF</EPol2>
<ComLockFuseRead>0</ComLockFuseRead>
<ResetDisable>1</ResetDisable>
</STK500>
<STK500_2><IspEnterProgMode><timeout>200</timeout><stabDelay>100</stabDelay><cmdexeDelay>25</cmdexeDelay><synchLoops>32</synchLoops><byteDelay>0</byteDelay><pollIndex>3</pollIndex><pollValue>0x53</pollValue></IspEnterProgMode><IspLeaveProgMode><preDelay>1</preDelay><postDelay>1</postDelay></IspLeaveProgMode><IspChipErase><eraseDelay>45</eraseDelay><pollMethod>1</pollMethod></IspChipErase><IspProgramFlash><mode>0x41</mode><blockSize>64</blockSize><delay>10</delay><cmd1>0x40</cmd1><cmd2>0x4C</cmd2><cmd3>0x00</cmd3><pollVal1>0x00</pollVal1><pollVal2>0x00</pollVal2></IspProgramFlash><IspProgramEeprom><mode>0x41</mode><blockSize>4</blockSize><delay>5</delay><cmd1>0xC1</cmd1><cmd2>0xC2</cmd2><cmd3>0x00</cmd3><pollVal1>0x00</pollVal1><pollVal2>0x00</pollVal2></IspProgramEeprom><IspReadFlash><blockSize>256</blockSize></IspReadFlash><IspReadEeprom><blockSize>256</blockSize></IspReadEeprom><IspReadFuse><pollIndex>4</pollIndex></IspReadFuse><IspReadLock><pollIndex>4</pollIndex></IspReadLock><IspReadSign><pollIndex>4</pollIndex></IspReadSign><IspReadOsccal><pollIndex>4</pollIndex></IspReadOsccal><HvspControlStack>0x4C 0x0C 0x1C 0x2C 0x3C 0x64 0x74 0x66 0x68 0x78 0x68 0x68 0x7A 0x6A 0x68 0x78 0x78 0x7D 0x6D 0x0C 0x80 0x40 0x20 0x10 0x11 0x08 0x04 0x02 0x03 0x08 0x04 0x00</HvspControlStack><HvspEnterProgMode><stabDelay>100</stabDelay><cmdexeDelay>0</cmdexeDelay><synchCycles>6</synchCycles><latchCycles>1</latchCycles><toggleVtg>1</toggleVtg><powoffDelay>25</powoffDelay><resetDelay1>1</resetDelay1><resetDelay2>0</resetDelay2></HvspEnterProgMode><HvspLeaveProgMode><stabDelay>100</stabDelay><resetDelay>25</resetDelay></HvspLeaveProgMode><HvspChipErase><pollTimeout>40</pollTimeout><eraseTime>0</eraseTime></HvspChipErase><HvspProgramFlash><mode>0x0D</mode><blockSize>256</blockSize><pollTimeout>5</pollTimeout></HvspProgramFlash><HvspReadFlash><blockSize>256</blockSize></HvspReadFlash><HvspProgramEeprom><mode>0x05</mode><blockSize>256</blockSize><pollTimeout>5</pollTimeout></HvspProgramEeprom><HvspReadEeprom><blockSize>256</blockSize></HvspReadEeprom><HvspProgramFuse><pollTimeout>25</pollTimeout></HvspProgramFuse><HvspProgramLock><pollTimeout>25</pollTimeout></HvspProgramLock></STK500_2><ICE50>
<MMU_ACCESS>
<MemTypeSram8Bit>0x05</MemTypeSram8Bit>
<MemTypeSram16Bit>0x0F</MemTypeSram16Bit>
<MemTypeSramShdw8Bit>0x0F</MemTypeSramShdw8Bit>
<MemTypeSramShdw16Bit>0x0F</MemTypeSramShdw16Bit>
<MemTypeEeprom>0x05</MemTypeEeprom>
<MemTypeProgram>0x05</MemTypeProgram>
<MemTypePrgEventBreak>0x05</MemTypePrgEventBreak>
<MemTypePrgEventTrigOut>0x05</MemTypePrgEventTrigOut>
<MemTypePrgEventTraceCtrl>0x05</MemTypePrgEventTraceCtrl>
<MemTypePrgEventComplex>0x05</MemTypePrgEventComplex>
<MemTypeSramEventLow>0x05</MemTypeSramEventLow>
<MemTypeSramEventHigh>0x05</MemTypeSramEventHigh>
<MemTypeEepromEvent>0x05</MemTypeEepromEvent>
<MemTypeRegisterEvent>0x0F</MemTypeRegisterEvent>
<MemTypeIoEvent>0x0F</MemTypeIoEvent>
<MemTypePreTrace>0x05</MemTypePreTrace>
<MemTypeTrace>0x15</MemTypeTrace>
<MemTypeCoreShdw>0x14</MemTypeCoreShdw>
<MemTypeCoreMem>0x14</MemTypeCoreMem>
</MMU_ACCESS>
<MMU_NOXRAM>
<MemTypeSram8Bit>0x0000015F</MemTypeSram8Bit>
<MemTypeSram16Bit>0x00000000</MemTypeSram16Bit>
<MemTypeSramShdw8Bit>0x00000000</MemTypeSramShdw8Bit>
<MemTypeSramShdw16Bit>0x00000000</MemTypeSramShdw16Bit>
<MemTypeEeprom>0x000000FF</MemTypeEeprom>
<MemTypeProgram>0x00000FFF</MemTypeProgram>
<MemTypePrgEventBreak>0x000007FF</MemTypePrgEventBreak>
<MemTypePrgEventTrigOut>0x000007FF</MemTypePrgEventTrigOut>
<MemTypePrgEventTraceCtrl>0x000007FF</MemTypePrgEventTraceCtrl>
<MemTypePrgEventComplex>0x000007FF</MemTypePrgEventComplex>
<MemTypeSramEventLow>0x0000015F</MemTypeSramEventLow>
<MemTypeSramEventHigh>0x0000FFFF</MemTypeSramEventHigh>
<MemTypeEepromEvent>0x000000FF</MemTypeEepromEvent>
<MemTypeRegisterEvent>0x00000000</MemTypeRegisterEvent>
<MemTypeIoEvent>0x00000000</MemTypeIoEvent>
<MemTypePreTrace>0x00000000</MemTypePreTrace>
<MemTypeTrace>0x0023FFFF</MemTypeTrace>
<MemTypeCoreShdw>0x00000FFF</MemTypeCoreShdw>
<MemTypeCoreMem>0x0000005F</MemTypeCoreMem>
</MMU_NOXRAM>
<DEFAULT_SETTINGS>
<ExtendedFuse>0xFE</ExtendedFuse>
<HighFuse>0xDF</HighFuse>
<LowFuse>0x62</LowFuse>
<Lockbit>0xff</Lockbit>
<ADDROSC>0x51</ADDROSC>
<VALOSC>0xC7</VALOSC>
<BINFILE>ATtiny25.bin</BINFILE>
<PARAM_MMU_DMEM_PARTION>0x02</PARAM_MMU_DMEM_PARTION>
<PARAM_MMU_MEMCFG>0x00</PARAM_MMU_MEMCFG>
<FREQUENCY>1000000</FREQUENCY>
<MAXFREQUENCY>20000000</MAXFREQUENCY>
<MINFREQUENCY>7</MINFREQUENCY>
<CLOCK>2 ; INTOSC = 1, INTRC=2;EXTCLK=4</CLOCK>
<TIMEROSC>1 ;NOTUSE = 1, EXTERNAL = 4, INTERNAL = 2 </TIMEROSC>
<XTAL2SOURCING>1 </XTAL2SOURCING>
<PARAM_AVR_RMR>0</PARAM_AVR_RMR>
<XRAMENABLE>0x40</XRAMENABLE>
<XRAMOTHER>0x40</XRAMOTHER>
<DIVCLOCK>8</DIVCLOCK>
<PARAM_OSC_WD_FREQ>0x80E8</PARAM_OSC_WD_FREQ>
</DEFAULT_SETTINGS>
<SETTINGS>
<CKOUT>
<TRUE>
<LFMASK>0x00000040</LFMASK>
<LFBITS>0x00000000</LFBITS>
<TEXT>CKOUT fuse</TEXT>
</TRUE>
<FALSE>
<LFMASK>0x00000040</LFMASK>
<LFBITS>0x00000040</LFBITS>
<TEXT>CKOUT fuse</TEXT>
</FALSE>
</CKOUT>
<SELFPRGEN>
<TRUE>
<LFMASK>0x00010000</LFMASK>
<LFBITS>0x00000000</LFBITS>
<TEXT>SELFPRGEN Fuse </TEXT>
</TRUE>
<FALSE>
<LFMASK>0x00010000</LFMASK>
<LFBITS>0x00010000</LFBITS>
<TEXT>SELFPRGEN Fuse </TEXT>
</FALSE>
</SELFPRGEN>
<CLOCK>
<STARTUP>
<INTOSC>
<OPT1>
<LFMASK>0x00000031</LFMASK>
<LFBITS>0x00000000</LFBITS>
<TEXT>258CK, 14CK +4.1ms</TEXT>
</OPT1>
<OPT2>
<LFMASK>0x00000031</LFMASK>
<LFBITS>0x00000010</LFBITS>
<TEXT>258CK, 14CK +65ms</TEXT>
</OPT2>
<OPT3>
<LFMASK>0x00000031</LFMASK>
<LFBITS>0x00000020</LFBITS>
<TEXT>1kCK, 14CK</TEXT>
</OPT3>
<OPT4>
<LFMASK>0x00000031</LFMASK>
<LFBITS>0x00000030</LFBITS>
<TEXT>1kCK, 14CK +4.1ms</TEXT>
</OPT4>
<OPT5>
<LFMASK>0x00000031</LFMASK>
<LFBITS>0x00000001</LFBITS>
<TEXT>1kCK, 14CK +65ms</TEXT>
</OPT5>
<OPT6>
<LFMASK>0x00000031</LFMASK>
<LFBITS>0x00000011</LFBITS>
<TEXT>16kCK, 14CK</TEXT>
</OPT6>
<OPT7>
<LFMASK>0x00000031</LFMASK>
<LFBITS>0x00000021</LFBITS>
<TEXT>16kCK, 14CK +4.1ms</TEXT>
</OPT7>
<OPT8>
<LFMASK>0x00000031</LFMASK>
<LFBITS>0x00000031</LFBITS>
<TEXT>16kCK, 14CK +65ms</TEXT>
</OPT8>
</INTOSC>
<INTRC>
<OPT1>
<LFMASK>0x00000030</LFMASK>
<LFBITS>0x00000000</LFBITS>
<TEXT>6 CK, 14CK</TEXT>
</OPT1>
<OPT2>
<LFMASK>0x00000030</LFMASK>
<LFBITS>0x00000010</LFBITS>
<TEXT>6 CK, 14CK+4ms</TEXT>
</OPT2>
<OPT3>
<LFMASK>0x00000030</LFMASK>
<LFBITS>0x00000020</LFBITS>
<TEXT>6 CK, 14CK+64 ms</TEXT>
</OPT3>
</INTRC>
<PLLCLK>
<OPT1>
<LFMASK>0x00000030</LFMASK>
<LFBITS>0x00000000</LFBITS>
<TEXT>1K CK, 14CK + 8ms</TEXT>
</OPT1>
<OPT2>
<LFMASK>0x00000030</LFMASK>
<LFBITS>0x00000010</LFBITS>
<TEXT>16K CK, 14CK + 8ms</TEXT>
</OPT2>
<OPT3>
<LFMASK>0x00000030</LFMASK>
<LFBITS>0x00000020</LFBITS>
<TEXT>1K CK, 14CK + 128ms</TEXT>
</OPT3>
<OPT4>
<LFMASK>0x00000030</LFMASK>
<LFBITS>0x00000030</LFBITS>
<TEXT>16K CK, 14CK + 128ms</TEXT>
</OPT4>
</PLLCLK>
<EXTCLK>
<OPT1>
<LFMASK>0x00000030</LFMASK>
<LFBITS>0x00000000</LFBITS>
<TEXT>6 CK, 14CK</TEXT>
</OPT1>
<OPT2>
<LFMASK>0x00000030</LFMASK>
<LFBITS>0x00000010</LFBITS>
<TEXT>6 CK, 14CK+4ms</TEXT>
</OPT2>
<OPT3>
<LFMASK>0x00000030</LFMASK>
<LFBITS>0x00000020</LFBITS>
<TEXT>6 CK, 14CK+64 ms</TEXT>
</OPT3>
</EXTCLK>
</STARTUP>
<CLOCK>
<INTOSC>
<LFMASK>0x0000000e</LFMASK>
<LFBITS>0x0000000e</LFBITS>
</INTOSC>
<PLLCLK>
<LFMASK>0x0000000f</LFMASK>
<LFBITS>0x00000001</LFBITS>
</PLLCLK>
<INTRC>
<OPT1>
<LFMASK>0x0000000f</LFMASK>
<LFBITS>0x00000002</LFBITS>
<TEXT>8</TEXT>
</OPT1>
<OPT2>
<LFMASK>0x0000000f</LFMASK>
<LFBITS>0x00000003</LFBITS>
<TEXT>6.4</TEXT>
</OPT2>
</INTRC>
<EXTCLK>
<LFMASK>0x0000000f</LFMASK>
<LFBITS>0x00000000</LFBITS>
</EXTCLK>
</CLOCK>
</CLOCK>
<WATCHDOG>
<TRUE>
<LFMASK>0x00001000</LFMASK>
<LFBITS>0x00000000</LFBITS>
<TEXT>Watchdog always ON</TEXT>
</TRUE>
<FALSE>
<LFMASK>0x00001000</LFMASK>
<LFBITS>0x00001000</LFBITS>
<TEXT>Watchdog disabled</TEXT>
</FALSE>
</WATCHDOG>
<RSTDISABLE>
<TRUE>
<LFMASK>0x00008000</LFMASK>
<LFBITS>0x00000000</LFBITS>
<TEXT>RSTDSBL Fuse </TEXT>
</TRUE>
<FALSE>
<LFMASK>0x00008000</LFMASK>
<LFBITS>0x00008000</LFBITS>
<TEXT>RSTDSBL</TEXT>
</FALSE>
</RSTDISABLE>
<CLKDIV>
<VALUE>8</VALUE>
<TRUE>
<LFMASK>0x00000080</LFMASK>
<LFBITS>0x00000000</LFBITS>
<TEXT>CKDIV8 Fuse</TEXT>
</TRUE>
<FALSE>
<LFMASK>0x00000080</LFMASK>
<LFBITS>0x00000080</LFBITS>
<TEXT>CKDIV8</TEXT>
</FALSE>
</CLKDIV>
<BOD>
<OPT1>
<LFMASK>0x00000700</LFMASK>
<LFBITS>0x00000700</LFBITS>
<TEXT>BOD disabled</TEXT>
</OPT1>
<OPT2>
<LFMASK>0x00000700</LFMASK>
<LFBITS>0x00000600</LFBITS>
<TEXT>BOD enabled, 1.8 V</TEXT>
</OPT2>
<OPT3>
<LFMASK>0x00000700</LFMASK>
<LFBITS>0x00000500</LFBITS>
<TEXT>BOD enabled, 2.7 V</TEXT>
</OPT3>
<OPT4>
<LFMASK>0x00000700</LFMASK>
<LFBITS>0x00000400</LFBITS>
<TEXT>BOD enabled, 4.3 V</TEXT>
</OPT4>
</BOD>
</SETTINGS>
</ICE50>
<AVRISPmkII/>
<AVRDragon/>
</ICE_SETTINGS></AVRPART>
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