## diffname alphapc/dma.c 1999/0415
## diff -e /dev/null /n/emeliedump/1999/0415/sys/src/brazil/alphapc/dma.c
0a
#include	"u.h"
#include	"../port/lib.h"
#include	"mem.h"
#include	"dat.h"
#include	"fns.h"
#include	"io.h"

typedef struct DMAport	DMAport;
typedef struct DMA	DMA;
typedef struct DMAxfer	DMAxfer;

enum
{
	/*
	 *  the byte registers for DMA0 are all one byte apart
	 */
	Dma0=		0x00,
	Dma0status=	Dma0+0x8,	/* status port */
	Dma0reset=	Dma0+0xD,	/* reset port */

	/*
	 *  the byte registers for DMA1 are all two bytes apart (why?)
	 */
	Dma1=		0xC0,
	Dma1status=	Dma1+2*0x8,	/* status port */
	Dma1reset=	Dma1+2*0xD,	/* reset port */
};

/*
 *  state of a dma transfer
 */
struct DMAxfer
{
	ulong	bpa;		/* bounce buffer physical address */
	void*	bva;		/* bounce buffer virtual address */
	void*	va;		/* virtual address destination/src */
	long	len;		/* bytes to be transferred */
	int	isread;
};

/*
 *  the dma controllers.  the first half of this structure specifies
 *  the I/O ports used by the DMA controllers.
 */
struct DMAport
{
	uchar	addr[4];	/* current address (4 channels) */
	uchar	count[4];	/* current count (4 channels) */
	uchar	page[4];	/* page registers (4 channels) */
	uchar	cmd;		/* command status register */
	uchar	req;		/* request registers */
	uchar	sbm;		/* single bit mask register */
	uchar	mode;		/* mode register */
	uchar	cbp;		/* clear byte pointer */
	uchar	mc;		/* master clear */
	uchar	cmask;		/* clear mask register */
	uchar	wam;		/* write all mask register bit */
};

struct DMA
{
	DMAport;
	int	shift;
	Lock;
	DMAxfer	x[4];
};

DMA dma[2] = {
	{ 0x00, 0x02, 0x04, 0x06,
	  0x01, 0x03, 0x05, 0x07,
	  0x87, 0x83, 0x81, 0x82,
	  0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
	 0 },

	{ 0xc0, 0xc4, 0xc8, 0xcc,
	  0xc2, 0xc6, 0xca, 0xce,
	  0x8f, 0x8b, 0x89, 0x8a,
	  0xd0, 0xd2, 0xd4, 0xd6, 0xd8, 0xda, 0xdc, 0xde,
	 1 },
};

/*
 *  DMA must be in the first 16MB.  This gets called early by the
 *  initialisation routines of any devices which require DMA to ensure
 *  the allocated bounce buffers are below the 16MB limit.
 */
void
dmainit(int chan)
{
	DMA *dp;
	DMAxfer *xp;
	ulong v;

	dp = &dma[(chan>>2)&1];
	chan = chan & 3;
	xp = &dp->x[chan];
	if(xp->bva != nil)
		return;

	v = (ulong)xalloc(BY2PG+BY2PG);
	if(v == 0 || PADDR(v) >= 16*MB){
		print("dmainit: chan %d: 0x%luX out of range\n", chan, v);
		xfree((void*)v);
		v = 0;
	}
	xp->bva = (void*)ROUND(v, BY2PG);
	xp->bpa = PADDR(xp->bva);
	xp->len = 0;
	xp->isread = 0;
}

/*
 *  setup a dma transfer.  if the destination is not in kernel
 *  memory, allocate a page for the transfer.
 *
 *  we assume BIOS has set up the command register before we
 *  are booted.
 *
 *  return the updated transfer length (we can't transfer across 64k
 *  boundaries)
 */
long
dmasetup(int chan, void *va, long len, int isread)
{
	DMA *dp;
	ulong pa;
	uchar mode;
	DMAxfer *xp;

	dp = &dma[(chan>>2)&1];
	chan = chan & 3;
	xp = &dp->x[chan];

	/*
	 *  if this isn't kernel memory or crossing 64k boundary or above 16 meg
	 *  use the allocated low memory page.
	 */
	pa = PADDR(va);
	if((((ulong)va)&0xF0000000) != KZERO
	|| (pa&0xFFFF0000) != ((pa+len)&0xFFFF0000)
	|| pa >= 16*MB) {
		if(xp->bva == nil)
			return -1;
		if(len > BY2PG)
			len = BY2PG;
		if(!isread)
			memmove(xp->bva, va, len);
		xp->va = va;
		xp->len = len;
		xp->isread = isread;
		pa = xp->bpa;
	}
	else
		xp->len = 0;

	/*
	 * this setup must be atomic
	 */
	ilock(dp);
	mode = (isread ? 0x44 : 0x48) | chan;
	outb(dp->mode, mode);	/* single mode dma (give CPU a chance at mem) */
	outb(dp->page[chan], pa>>16);
	outb(dp->cbp, 0);		/* set count & address to their first byte */
	outb(dp->addr[chan], pa>>dp->shift);		/* set address */
	outb(dp->addr[chan], pa>>(8+dp->shift));
	outb(dp->count[chan], (len>>dp->shift)-1);		/* set count */
	outb(dp->count[chan], ((len>>dp->shift)-1)>>8);
	outb(dp->sbm, chan);		/* enable the channel */
	iunlock(dp);

	return len;
}

int
dmadone(int chan)
{
	DMA *dp;

	dp = &dma[(chan>>2)&1];
	chan = chan & 3;

	return inb(dp->cmd) & (1<<chan);
}

/*
 *  this must be called after a dma has been completed.
 *
 *  if a page has been allocated for the dma,
 *  copy the data into the actual destination
 *  and free the page.
 */
void
dmaend(int chan)
{
	DMA *dp;
	DMAxfer *xp;

	dp = &dma[(chan>>2)&1];
	chan = chan & 3;

	/*
	 *  disable the channel
	 */
	ilock(dp);
	outb(dp->sbm, 4|chan);
	iunlock(dp);

	xp = &dp->x[chan];
	if(xp->len == 0 || !xp->isread)
		return;

	/*
	 *  copy out of temporary page
	 */
	memmove(xp->va, xp->bva, xp->len);
	xp->len = 0;
}

/*
int
dmacount(int chan)
{
	int     retval;
	DMA     *dp;
 
	dp = &dma[(chan>>2)&1];
	outb(dp->cbp, 0);
	retval = inb(dp->count[chan]);
	retval |= inb(dp->count[chan]) << 8;
	return((retval<<dp->shift)+1);
}
 */
.
## diffname alphapc/dma.c 1999/0423
## diff -e /n/emeliedump/1999/0415/sys/src/brazil/alphapc/dma.c /n/emeliedump/1999/0423/sys/src/brazil/alphapc/dma.c
165a
	outb(dp->page[chan], pa>>16);
outb(0x400|dp->page[chan], pa>>24);
.
163a
	outb(dp->mode, mode);	/* single mode dma (give CPU a chance at mem) */
.
161,162c
	ilock(dp);
.
159d
154a
#else
	pa = PCIWADDR(va);
#endif /* notdef */
.
144,145c
		if(len > xp->blen)
			len = xp->blen;
.
137a
#ifdef notdef
.
136c
	 *  use the bounce buffer.
.
109a

	return 0;
.
107a
	if(xp->bpa >= 16*MB){
		/*
		 * This will panic with the current
		 * implementation of xspanalloc().
		xfree(xp->bva);
		 */
		xp->bva = nil;
		return 1;
	}
	xp->blen = maxtransfer;
.
106c

	xp->bva = xspanalloc(maxtransfer, BY2PG, 64*1024);
	if(xp->bva == nil)
		return 1;
.
97,104c
	if(xp->bva != nil){
		if(xp->blen < maxtransfer)
			return 1;
		return 0;
.
93a
	if(maxtransfer > 64*1024)
		maxtransfer = 64*1024;

.
92d
87,88c
int
dmainit(int chan, int maxtransfer)
.
35a
	int	blen;		/* bounce buffer length */
.
12,28d
## diffname alphapc/dma.c 1999/0424
## diff -e /n/emeliedump/1999/0423/sys/src/brazil/alphapc/dma.c /n/emeliedump/1999/0424/sys/src/brazil/alphapc/dma.c
208a

{ int i;
outb(dp->cbp, 0);
i = inb(dp->addr[chan]);
i |= inb(dp->addr[chan])<<8;
i |= inb(dp->page[chan])<<16;
i |= inb(0x400|dp->page[chan])<<24;
print("X%uX+", i);
}
.
171a
print("pa%lux+", pa);
.
167c
//outb(0x400|dp->page[chan], pa>>24);
.
154c
	pa = ISAWADDR(va);
.
134a
print("va%lux+", va);
.
## diffname alphapc/dma.c 1999/0501
## diff -e /n/emeliedump/1999/0424/sys/src/brazil/alphapc/dma.c /n/emeliedump/1999/0501/sys/src/brazil/alphapc/dma.c
218c
//print("X%uX+", i);
.
173c
//print("pa%lux+", pa);
.
168c
#ifdef tryPCI
	outb(0x400|dp->page[chan], pa>>24);
#endif /* tryPCI */
.
156a
#ifdef tryISA
	pa = ISAWADDR(va);
#endif /* tryISA */
#ifdef tryPCI
	pa = PCIWADDR(va);
#endif /* tryPCI */
.
154,155d
135,136d
128a
//print("va%lux+", va);
#define tryPCI
#ifdef notdef
.
87a
outb(dp->mc, 0);
.
## diffname alphapc/dma.c 1999/0504
## diff -e /n/emeliedump/1999/0501/sys/src/brazil/alphapc/dma.c /n/emeliedump/1999/0504/sys/src/brazil/alphapc/dma.c
219,227d
212a
dmastatus(dp, chan);
.
181c
dmastatus(dp, chan);
.
176a
	outb(dp->cbp, 0);		/* set count & address to their first byte */
.
109a
static void
dmastatus(DMA *dp, int chan)
{
	int a, l, s;

	ilock(dp);
	outb(dp->cbp, 0);
	a = inb(dp->addr[chan]);
	a |= inb(dp->addr[chan])<<8;
	a |= inb(dp->page[chan])<<16;
	a |= inb(0x400|dp->page[chan])<<24;
	outb(dp->cbp, 0);
	l = inb(dp->count[chan]);
	l |= inb(dp->count[chan])<<8;
	s = inb(dp->cmd);
	iunlock(dp);
	print("addr %uX len %uX stat %uX\n", a, l, s);
}

void
xdmastatus(int chan)
{
	DMA *dp;

	dp = &dma[(chan>>2)&1];
	chan = chan & 3;

	dmastatus(dp, chan);
}

.
## diffname alphapc/dma.c 1999/0505
## diff -e /n/emeliedump/1999/0504/sys/src/brazil/alphapc/dma.c /n/emeliedump/1999/0505/sys/src/brazil/alphapc/dma.c
244c
dmastatus(dp, chan, 'E');
.
212c
dmastatus(dp, chan, 'S');
.
137c
	dmastatus(dp, chan, 'X');
.
126c
	print("%c: addr %uX len %uX stat %uX\n", c, a, l, s);
.
111c
dmastatus(DMA *dp, int chan, char c)
.
## diffname alphapc/dma.c 1999/0506
## diff -e /n/emeliedump/1999/0505/sys/src/brazil/alphapc/dma.c /n/emeliedump/1999/0506/sys/src/brazil/alphapc/dma.c
244c
//dmastatus(dp, chan, 'E');
.
212c
//dmastatus(dp, chan, 'S');
.
161a
#ifndef PCIWADDR
#define PCIWADDR(va)	PADDR(va)
#endif /* PCIWADDR */
.
110,128d
88c
//dmastatus(dp, chan, 'I');
.
76a
	if(once == 0){
		outb(dma[0].mc, 0);
		outb(dma[1].mc, 0);
		outb(dma[0].cmask, 0);
		outb(dma[1].cmask, 0);
		outb(dma[1].mode, 0xC0);
		once = 1;
	}

.
75a
	static int once;
.
65a
static void
dmastatus(DMA *dp, int chan, char c)
{
	int a, l, s;

	ilock(dp);
	outb(dp->cbp, 0);
	a = inb(dp->addr[chan]);
	a |= inb(dp->addr[chan])<<8;
	a |= inb(dp->page[chan])<<16;
	a |= inb(0x400|dp->page[chan])<<24;
	outb(dp->cbp, 0);
	l = inb(dp->count[chan]);
	l |= inb(dp->count[chan])<<8;
	s = inb(dp->cmd);
	iunlock(dp);
	print("%c: addr %uX len %uX stat %uX\n", c, a, l, s);
}

.
6d
## diffname alphapc/dma.c 1999/0507
## diff -e /n/emeliedump/1999/0506/sys/src/brazil/alphapc/dma.c /n/emeliedump/1999/0507/sys/src/brazil/alphapc/dma.c
203a
	if((((ulong)va)&0xF0000000) != KZERO){
		if(xp->bva == nil)
			return -1;
		if(len > xp->blen)
			len = xp->blen;
		if(!isread)
			memmove(xp->bva, va, len);
		xp->va = va;
		xp->len = len;
		xp->isread = isread;
		pa = PCIWADDR(xp->bva);
	}
	else
		xp->len = 0;
.
175d
168a
	xp = &dp->x[chan];
.
6a
#include	"io.h"

.
## diffname alphapc/dma.c 2000/0401
## diff -e /n/emeliedump/1999/0507/sys/src/brazil/alphapc/dma.c /n/emeliedump/2000/0401/sys/src/9/alphapc/dma.c
98a
		if(ioalloc(0x00, 0x10, 0, "dma") < 0
		|| ioalloc(0x80, 0x10, 0, "dma") < 0
		|| ioalloc(0xd0, 0x10, 0, "dma") < 0)
			panic("dmainit");
.
## diffname alphapc/dma.c 2001/1208
## diff -e /n/emeliedump/2000/0401/sys/src/9/alphapc/dma.c /n/emeliedump/2001/1208/sys/src/9/alphapc/dma.c
276c
dmastatus(dp, chan, 'E');
.
244c
dmastatus(dp, chan, 'S');
.
122c
dmastatus(dp, chan, 'I');
.
## diffname alphapc/dma.c 2001/1210
## diff -e /n/emeliedump/2001/1208/sys/src/9/alphapc/dma.c /n/emeliedump/2001/1210/sys/src/9/alphapc/dma.c
276c
//dmastatus(dp, chan, 'E');
.
244c
//dmastatus(dp, chan, 'S');
.
122c
//dmastatus(dp, chan, 'I');
.