## diffname mtx/mem.h 2001/0810
## diff -e /dev/null /n/emeliedump/2001/0810/sys/src/9/mtx/mem.h
0a
/* none of this is meant to be correct yet */
/*
* Memory and machine-specific definitions. Used in C and assembler.
*/
/*
* Sizes
*/
#define BI2BY 8 /* bits per byte */
#define BI2WD 32 /* bits per word */
#define BY2WD 4 /* bytes per word */
#define BY2V 8 /* bytes per vlong */
#define BY2PG 8192 /* bytes per page */
#define WD2PG (BY2PG/BY2WD) /* words per page */
#define PGSHIFT 13 /* log(BY2PG) */
#define ROUND(s, sz) (((s)+(sz-1))&~(sz-1))
#define PGROUND(s) ROUND(s, BY2PG)
#define BLOCKALIGN 8
#define BY2PTE 8 /* bytes per pte entry */
#define PTE2PG (BY2PG/BY2PTE) /* pte entries per page */
#define MAXMACH 1 /* max # cpus system can run */
#define KSTACK 4096 /* Size of kernel stack */
/*
* Time
*/
#define HZ 100 /* clock frequency */
#define MS2HZ (1000/HZ)
#define TK2SEC(t) ((t)/HZ) /* ticks to seconds */
#define MS2TK(t) (((t)*HZ+500)/1000) /* milliseconds to closest tick */
/*
* Magic registers
*/
#define MACH 30 /* R30 is m-> */
#define USER 29 /* R29 is up-> */
/*
* Fundamental addresses
*/
#define UREGSIZE ((8+32)*4)
/*
* MMU
*
*/
/* L1 table entry and Mx_TWC flags */
#define PTEVALID (1<<0)
#define PTEWT (1<<1) /* write through */
#define PTE4K (0<<2)
#define PTE512K (1<<2)
#define PTE8MB (3<<2)
#define PTEG (1<<4) /* guarded */
/* L2 table entry and Mx_RPN flags (also PTEVALID) */
#define PTECI (1<<1) /* cache inhibit */
#define PTESH (1<<2) /* page is shared; ASID ignored */
#define PTELPS (1<<3) /* large page size */
#define PTEWRITE 0x9F0
/* TLB and MxEPN flag */
#define TLBVALID (1<<9)
#define TLBSETS 32 /* number of tlb sets (603/603e) */
#define PTEMAPMEM (1024*1024)
#define PTEPERTAB (PTEMAPMEM/BY2PG)
#define SEGMAPSIZE 512
#define SSEGMAPSIZE 16
/*
* Address spaces
*/
#define UZERO 0 /* base of user address space */
#define UTZERO (UZERO+BY2PG) /* first address in user text */
#define USTKTOP (TSTKTOP-TSTKSIZ*BY2PG) /* byte just beyond user stack */
#define TSTKTOP KZERO /* top of temporary stack */
#define TSTKSIZ 100
#define KZERO 0x80000000 /* base of kernel address space */
#define KTZERO (KZERO+0x400000) /* first address in kernel text */
#define USTKSIZE (4*1024*1024) /* size of user stack */
#define PCI1 0x40000000
#define PCI0 0xfd000000
#define IOMEM 0xfe000000
#define FALCON 0xfef80000
#define RAVEN 0xfeff0000
#define FLASHA 0xff000000
#define FLASHB 0xff800000
#define FLASHAorB 0xfff00000
#define isphys(x) (((ulong)x&KZERO)!=0)
.
## diffname mtx/mem.h 2001/1122
## diff -e /n/emeliedump/2001/0810/sys/src/9/mtx/mem.h /n/emeliedump/2001/1122/sys/src/9/mtx/mem.h
101a
/*
* standard ppc special purpose registers
*/
#define DSISR 18
#define DAR 19 /* Data Address Register */
#define DEC 22 /* Decrementer */
#define SRR0 26 /* Saved Registers (exception) */
#define SRR1 27
#define SPRG0 272 /* Supervisor Private Registers */
#define SPRG1 273
#define SPRG2 274
#define SPRG3 275
#define TBRU 269 /* Time base Upper/Lower (Reading) */
#define TBRL 268
#define TBWU 284 /* Time base Upper/Lower (Writing) */
#define TBWL 285
#define PVR 287 /* Processor Version */
.
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68a
#define PTEKERNEL (0<<2)
#define PTEUSER (1<<2)
#define PTESIZE (1<<7)
#define NTLBPID 16
#define TLBPID(n) ((n)&(NTLBPID-1))
/* soft tlb */
#define STLBLOG 12
#define STLBSIZE (1<<STLBLOG)
/*
* portable MMU bits for fault.c - though still machine specific
*/
//#define PTEVALID (MMUPP|MMUV)
#define PTEWRITE (2<<10)
#define PTERONLY (3<<10)
#define PTEUNCACHED (1<<4)
/*
* physical MMU bits
*/
.
67c
//#define PTEWRITE 0x9F0
.
52d
46a
#define MACHADDR (KTZERO-MAXMACH*MACHSIZE)
#define MACHP(n) ((Mach *)(MACHADDR+(n)*MACHSIZE))
.
44a
* virtual MMU
*/
#define PTEMAPMEM (1024*1024)
#define PTEPERTAB (PTEMAPMEM/BY2PG)
#define SEGMAPSIZE 1984
#define SSEGMAPSIZE 16
#define PPN(x) ((x)&~(BY2PG-1))
/*
.
36a
* Exception codes (trap vectors)
*/
#define CRESET 0x01
#define CMCHECK 0x02
#define CDSI 0x03
#define CISI 0x04
#define CEI 0x05
#define CALIGN 0x06
#define CPROG 0x07
#define CFPU 0x08
#define CDEC 0x09
#define CSYSCALL 0x0C
#define CTRACE 0x0D
// #define CFPA 0x0E
/* rest are power-implementation dependent */
#define CIMISS 0x10
#define CDLMISS 0x11
#define CDSMISS 0x12
#define CIBREAK 0x13
#define CSMI 0x14
/*
.
35a
/* Bit encodings for Machine State Register (MSR) */
#define MSR_POW (1<<18) /* Enable Power Management */
#define MSR_TGPR (1<<17) /* TLB Update registers in use */
#define MSR_ILE (1<<16) /* Interrupt Little-Endian enable */
#define MSR_EE (1<<15) /* External Interrupt enable */
#define MSR_PR (1<<14) /* Supervisor/User privelege */
#define MSR_FP (1<<13) /* Floating Point enable */
#define MSR_ME (1<<12) /* Machine Check enable */
#define MSR_FE0 (1<<11) /* Floating Exception mode 0 */
#define MSR_SE (1<<10) /* Single Step */
#define MSR_BE (1<<9) /* Branch Trace */
#define MSR_FE1 (1<<8) /* Floating Exception mode 1 */
#define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */
#define MSR_IR (1<<5) /* Instruction MMU enable */
#define MSR_DR (1<<4) /* Data MMU enable */
#define MSR_RI (1<<1) /* Recoverable Exception */
#define MSR_LE (1<<0) /* Little-Endian enable */
#define MSR_ MSR_FP|MSR_FE0|MSR_FE1|MSR_ME
.
33a
#define TK2MS(t) ((t)*MS2HZ) /* ticks to milliseconds */
.
25a
#define MACHSIZE BY2PG
.
24a
//#define BY2PTE 8 /* bytes per pte entry */
//#define PTE2PG (BY2PG/BY2PTE) /* pte entries per page */
.
22,23c
#define MHz 1000000
.
20c
#define CACHELINELOG 4
#define CACHELINESZ (1<<CACHELINELOG)
#define BLOCKALIGN CACHELINESZ
.
17c
#define PGSHIFT 12 /* log(BY2PG) */
.
15c
#define BY2PG 4096 /* bytes per page */
.
1,2d
## diffname mtx/mem.h 2001/1205
## diff -e /n/emeliedump/2001/1122/sys/src/9/mtx/mem.h /n/emeliedump/2001/1205/sys/src/9/mtx/mem.h
176,193d
94c
#define PTEPERTAB (PTEMAPMEM/BY2PG)
.
81a
/* PPC604e-specific: */
#define CPERF 0x0F /* performance monitoring */
#define CIBREAK 0x13
#define CSMI 0x14
// left over from 603?
// #define CIMISS 0x10
// #define CDLMISS 0x11
// #define CDSMISS 0x12
.
63,80c
#define CRESET 0x01
#define CMCHECK 0x02
#define CDSI 0x03
#define CISI 0x04
#define CEI 0x05
#define CALIGN 0x06
#define CPROG 0x07
#define CFPU 0x08
#define CDEC 0x09
#define CSYSCALL 0x0C
#define CTRACE 0x0D /* optional */
#define CFPA 0x0E /* optional */
.
60a
* PPC604e-specific Special Purpose Registers (OEA)
*/
#define HID0 1008 /* Hardware Implementation Dependant Register 0 */
#define HID1 1009 /* Hardware Implementation Dependant Register 1 */
#define PMC1 953 /* Performance Monitor Counter 1 */
#define PMC2 954 /* Performance Monitor Counter 2 */
#define PMC3 957 /* Performance Monitor Counter 3 */
#define PMC4 958 /* Performance Monitor Counter 4 */
#define MMCR0 952 /* Monitor Control Register 0 */
#define MMCR1 956 /* Monitor Control Register 0 */
#define SIA 955 /* Sampled Instruction Address */
#define SDA 959 /* Sampled Data Address */
#define BIT(i) (1<<(32-(i))) /* Silly backwards register bit numbering scheme */
/*
* Bit encodings for Machine State Register (MSR)
*/
#define MSR_POW BIT(13) /* Enable Power Management */
#define MSR_ILE BIT(15) /* Interrupt Little-Endian enable */
#define MSR_EE BIT(16) /* External Interrupt enable */
#define MSR_PR BIT(17) /* Supervisor/User privelege */
#define MSR_FP BIT(18) /* Floating Point enable */
#define MSR_ME BIT(19) /* Machine Check enable */
#define MSR_FE0 BIT(20) /* Floating Exception mode 0 */
#define MSR_SE BIT(21) /* Single Step (optional) */
#define MSR_BE BIT(22) /* Branch Trace (optional) */
#define MSR_FE1 BIT(23) /* Floating Exception mode 1 */
#define MSR_IP BIT(25) /* Exception prefix 0x000/0xFFF */
#define MSR_IR BIT(26) /* Instruction MMU enable */
#define MSR_DR BIT(27) /* Data MMU enable */
#define MSR_RI BIT(30) /* Recoverable Exception */
#define MSR_LE BIT(31) /* Little-Endian enable */
/*
.
58c
#define IBATU(i) (528+2*(i)) /* Instruction BAT register (upper) */
#define IBATL(i) (529+2*(i)) /* Instruction BAT register (lower) */
#define DBATU(i) (536+2*(i)) /* Data BAT register (upper) */
#define DBATL(i) (537+2*(i)) /* Data BAT register (lower) */
.
40,56c
/*
* Standard PPC Special Purpose Registers (OEA and VEA)
*/
#define DSISR 18
#define DAR 19 /* Data Address Register */
#define DEC 22 /* Decrementer */
#define SDR1 25
#define SRR0 26 /* Saved Registers (exception) */
#define SRR1 27
#define SPRG0 272 /* Supervisor Private Registers */
#define SPRG1 273
#define SPRG2 274
#define SPRG3 275
#define ASR 280 /* Address Space Register */
#define EAR 282 /* External Access Register (optional) */
#define TBRU 269 /* Time base Upper/Lower (Reading) */
#define TBRL 268
#define TBWU 284 /* Time base Upper/Lower (Writing) */
#define TBWL 285
#define PVR 287 /* Processor Version */
#define IABR 1010 /* Instruction Address Breakpoint Register (optional) */
#define DABR 1013 /* Data Address Breakpoint Register (optional) */
#define FPECR 1022 /* Floating-Point Exception Cause Register (optional) */
#define PIR 1023 /* Processor Identification Register (optional) */
.
## diffname mtx/mem.h 2001/1207
## diff -e /n/emeliedump/2001/1205/sys/src/9/mtx/mem.h /n/emeliedump/2001/1207/sys/src/9/mtx/mem.h
224a
#define getpgcolor(a) 0
.
84c
#define BIT(i) (1<<(31-(i))) /* Silly backwards register bit numbering scheme */
.
## diffname mtx/mem.h 2001/1208
## diff -e /n/emeliedump/2001/1207/sys/src/9/mtx/mem.h /n/emeliedump/2001/1208/sys/src/9/mtx/mem.h
211,212c
//#define KZERO 0x80000000 /* base of kernel address space */
#define KZERO 0
#define KTZERO (KZERO+0x4000) /* first address in kernel text */
.
151c
#define MACHADDR (KZERO+0x2000)
.
## diffname mtx/mem.h 2001/1212
## diff -e /n/emeliedump/2001/1208/sys/src/9/mtx/mem.h /n/emeliedump/2001/1212/sys/src/9/mtx/mem.h
211,214c
#define KZERO 0x80000000 /* base of kernel address space */
#define KTZERO (KZERO+0x4000) /* first address in kernel text */
#define USTKSIZE (4*1024*1024) /* size of user stack */
#define UREGSIZE ((8+32)*4)
.
181,184d
149,156d
126,130d
27c
#define MAXMACH 1 /* max # cpus system can run */
.
24,25c
#define BY2PTE 8 /* bytes per pte entry */
#define PTE2PG (BY2PG/BY2PTE) /* pte entries per page */
.
19,20c
#define CACHELINESZ (1<<CACHELINELOG)
#define BLOCKALIGN CACHELINESZ
.
## diffname mtx/mem.h 2001/1215
## diff -e /n/emeliedump/2001/1212/sys/src/9/mtx/mem.h /n/emeliedump/2001/1215/sys/src/9/mtx/mem.h
201a
#define IOSIZE 0x00800000
.
199,200c
#define PCIMEM0 0xf0000000
#define PCISIZE0 0x0e000000
#define PCIMEM1 0xc0000000
#define PCISIZE1 0x30000000
.
## diffname mtx/mem.h 2002/0108
## diff -e /n/emeliedump/2001/1215/sys/src/9/mtx/mem.h /n/emeliedump/2002/0108/sys/src/9/mtx/mem.h
146,183c
#define PTEVALID 0 /* implied for putmmu -- real V bit in first pte word */
#define PTEWRITE 2
#define PTERONLY 3
#define PTEUNCACHED BIT(26)
.
144c
* Second pte word, known by fault.c, passed to putmmu()
.
## diffname mtx/mem.h 2002/0112
## diff -e /n/emeliedump/2002/0108/sys/src/9/mtx/mem.h /n/emeliedump/2002/0112/sys/src/9/mtx/mem.h
141a
/*
* First pte word
*/
#define PTE0(v, vsid, h, va) (((v)<<31)|((vsid)<<7)|((h)<<6)|(((va)>>22)&0x3f))
.
25c
#define BY2PTEG 64 /* bytes per pte group */
.
## diffname mtx/mem.h 2002/0116
## diff -e /n/emeliedump/2002/0112/sys/src/9/mtx/mem.h /n/emeliedump/2002/0116/sys/src/9/mtx/mem.h
151,154c
#define PTE1_W BIT(25)
#define PTE1_I BIT(26)
#define PTE1_M BIT(27)
#define PTE1_G BIT(28)
#define PTE1_RW BIT(30)
#define PTE1_RO BIT(31)
/*
* PTE bits for fault.c. These belong to the second PTE word. Validity is
* implied for putmmu(), and we always set PTE0_V. PTEVALID is used
* here to set cache policy bits on a global basis.
*/
#define PTEVALID 0
#define PTEWRITE PTE1_RW
#define PTERONLY PTE1_RO
#define PTEUNCACHED PTE1_I
.
149c
* Second pte word; WIMG & PP(RW/RO) common to page table and BATs
.
## diffname mtx/mem.h 2002/0125
## diff -e /n/emeliedump/2002/0116/sys/src/9/mtx/mem.h /n/emeliedump/2002/0125/sys/src/9/mtx/mem.h
101a
#define MSR_PM BIT(29) /* Performance Monitor marked mode (604e specific) */
.
## diffname mtx/mem.h 2002/0326
## diff -e /n/emeliedump/2002/0125/sys/src/9/mtx/mem.h /n/emeliedump/2002/0326/sys/src/9/mtx/mem.h
38d
## diffname mtx/mem.h 2002/0710
## diff -e /n/emeliedump/2002/0326/sys/src/9/mtx/mem.h /n/emeliedump/2002/0710/sys/src/9/mtx/mem.h
37d
35d
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